HFC-SPCI Cologne Chip AG, HFC-SPCI Datasheet - Page 35

• Manufacturer Part Number: HFC-SPCI
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

RESET sets register MST_EMOD to all '0's.
6URbeQbi !)))
Name
MST_EMOD
C/I
TRxR
Addr.
B4h
0Ch
08h
Bits
5..3
3..0
7..4
5..2
0
1
2
6
7
0
1
6
7
r/w Function
r/w on read: indication
w
w
w
w
w
w
r
r
r
r
r
slow down C4IO clock adjustment (see Figure 17)
'0' C4IO clock is adjusted in the 31th time slot twice for one
'1' C4IO clock is adjusted in the 31th time slot once for one
enable/disable AUX channel mirroring
'0' normal opration (reset default)
'1' disable AUX channel data mirroring
unused
select D-channel data flow (see also: CONNECT register)
bit 3: '0'
bit 4: '0'
bit 5: '0'
unused
enable GCI/IOM2 write slots
'0' disable GCI/IOM2 write slots; slot #2 and slot #3 may be
'1' enables slot #2 and slot #3 as master, D- and C/I-channel
on write: command
unused
'1' monitor receive ready (2 bytes received)
This bit is reset after read of second monitor byte (MON2_D)
'1' Monitor transmitter ready
Writing on MON2_D starts transmisssion and resets this bit.
reserved
STIO2 in
STIO1 in
half clock cycle (reset default)
half clock cycle
used for normal data
'1'
'1'
'1'
destination
D-HFC
D-HFC
D-S/T
D-S/T
D-GCI/IOM2
D-GCI/IOM2
source
D-S/T
D-GCI/IOM2
D-HFC
D-GCI/IOM2
D-HFC
D-S/T
#% _V &$