HFC-SPCI Cologne Chip AG, HFC-SPCI Datasheet - Page 4

• Manufacturer Part Number: HFC-SPCI
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

7 S/T interface circuitry ........................................................................................................................... 49
7.1 External receiver circuitry .................................................................................................................... 49
7.2 External transmitter circuitry................................................................................................................ 50
7.3 Oscillator circuitry ................................................................................................................................ 53
7.4 EEPROM circuitry................................................................................................................................ 53
7.5 PME pin circuitry.................................................................................................................................. 54
8 State matrices for NT and TE............................................................................................................... 55
8.1 S/T interface activation/deactivation layer 1 for finite state matrix for NT ......................................... 55
8.2 Activation/deactivation layer 1 for finite state matrix for TE .............................................................. 56
9 Binary organisation of the frames........................................................................................................ 57
9.1 S/T frame structure ............................................................................................................................... 57
9.2 GCI frame structure .............................................................................................................................. 58
10 Clock synchronisation ......................................................................................................................... 59
10.1 Clock synchronisation in NT-mode .................................................................................................... 59
10.2 Clock synchronisation in TE-mode .................................................................................................... 60
11 HFC-S PCI package dimensions ........................................................................................................ 61
12 ISDN PCI card sample circuitry with HFC-S PCI........................................................................... 62
Figures
Figure 1: HFC-S PCI block diagram............................................................................................................. 7
Figure 2: Pin Connection .............................................................................................................................. 8
Figure 3: HFC-S PCI in I/O address mapped mode.................................................................................... 17
Figure 4: HFC-S PCI in memory address mapped mode............................................................................ 17
Figure 5: FIFO Organisation (shown for B-channel, similar for D-channel) ............................................. 25
Figure 6: FIFO Data Organisation .............................................................................................................. 27
Figure 7: Function of the CONNECT register bits..................................................................................... 36
Figure 8: GCI/IOM2 bus clock and data alignment.................................................................................... 46
Figure 9: External receiver circuitry........................................................................................................... 49
Figure 10: External transmitter circuitry .................................................................................................... 50
Figure 11: Oscillator Circuitry.................................................................................................................... 53
Figure 12: EEPROM circuitry .................................................................................................................... 53
Figure 13: PME pin circuitry ...................................................................................................................... 54
Figure 14: Frame structure at reference point S and T ............................................................................... 57
Figure 15: Single channel GCI format........................................................................................................ 58
Figure 16: Clock synchronisation in NT-mode .......................................................................................... 59
Figure 17: Clock synchronisation in TE-mode ........................................................................................... 60
Figure 18: HFC-S PCI package dimensions ............................................................................................... 61
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