HFC-SPCI Cologne Chip AG, HFC-SPCI Datasheet - Page 26

• Manufacturer Part Number: HFC-SPCI
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

In the send channels F1 is only changed from the PC interface side if the software driver wants to say
„end of send frame“. Then the current value of Z1 is stored, F1 is incremented and Z1 is used as start
address of the next frame. Z1(F2) and Z2(F2) can not be accessed.
3.4.3.2 Automatically D-channel frame repetition
The D-channel send FIFO has a special feature. If the S/T interface signals a D-channel contention
before the CRC is sent the Z2 counter is set to the starting address of the current frame and the HFC-S
PCI tries to repeat the frame automatically.
3.4.3.3 FIFO full condition in send channels
FIFO full condition can easily be calculated from the Z1/Z2 table in the Memory Window.
Remember that an increment of Z-value 1FFFh is 0200h in the B-channels!
There are two different FIFO full conditions. The first one is met when the FIFO contents comes up to 31
frames (B-channel) or 15 frames (D-channel). There is no possibility for the HFC-S PCI to manage more
frames even if the frames are very small.
The second limitation is the size of the FIFO which is 512 byte for the D-channel and 7.5 KByte for the
B-channels.
3.4.3.4 Receive Channels (B1, B2 and D receive)
The receive channels receive data from the S/T or GCI/IOM2 bus interface read registers. The data is
converted from HDLC into plain data and sent to the FIFO. The data can then be read via the host bus
interface.
The HFC-S PCI checks the HDLC data coming in. If it finds a flag or more than 5 consecutive 1s it does
not generate any output data. In this case Z1 is not incremented. Proper HDLC data being received is
converted by the HFC-S PCI into plain data. After the ending flag of a frame the HFC-S PCI checks the
HDLC CRC checksum. If it is correct one byte with all 0s is inserted behind the CRC data in the FIFO
named STAT. This last byte of a frame in the FIFO is different from all 0s if there is no correct CRC
field at the end of the frame.
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The HFC-S PCI begins to transmit bytes from a FIFO at the moment Z1 Z2. So if the Z1 pointer
is updated by software after writing the transmit data into the FIFO space of the Memory Window
the transmission starts.
important!
6URbeQbi !)))