HFC-SPCI Cologne Chip AG, HFC-SPCI Datasheet - Page 33

• Manufacturer Part Number: HFC-SPCI
• Description: Isdn S/t HDLC Basic Rate Controller
• Manufacturer: Cologne Chip AG

4.2
Timeslots for transmit direction
Timeslots for receive direction
Data registers
6URbeQbi !)))
Name
B1_SSL
B2_SSL
AUX1_SSL
AUX2_SSL
Name
B1_RSL
B2_RSL
AUX1_RSL
AUX2_RSL
Name
B1_D
B2_D
AUX1_D
AUX2_D
*
Enabling more than one channel on the same slot causes undefined output data.
*
If the data registers AUX1_D and AUX2_D are not overwritten, the transmisson slots AUX1_SSL
and AUX2_SSL mirror the data received in AUX1_RSL and AUX2_RSL slots. This is useful for
an internal connection between two CODECs. This mirroring is disabled by setting bit 1 in
MST_EMOD register
important!
note!
Register bit description of GCI/IOM2 bus section
Addr.
Addr.
Addr.
ACh
8Ch
9Ch
A0h
A4h
A8h
80h
84h
88h
90h
94h
98h
Bits
Bits
Bits
4..0
4..0
0..7
5
6
7
5
6
7
r/w Function
r/w Function
r/w Function
r/w read/write data registers for selected timeslot data
w
w
w
w
w
w
w
w
select GCI/IOM2 bus transmission slot (0..31)
unused
select GCI/IOM2 bus data lines
'0' STIO1 output
'1' STIO2 output
transmit channel enable for GCI/IOM2 bus
'0' disable (reset default)
'1' enable
select GCI/IOM2 bus receive slot (0..31)
unused
select GCI/IOM2 bus data lines
'0' STIO2 is input
'1' STIO1 is input
receive channel enable for GCI/IOM2 bus
'0' disable (reset default)
'1' enable
## _V &$