XR16L784 Exar Corporation, XR16L784 Datasheet - Page 8

• Manufacturer Part Number: XR16L784
• Description: High Performance 5V And 3.3V Quad Uart
• Manufacturer: Exar Corporation

XR16L784
HIGH PERFORMANCE 5V AND 3.3V QUAD UART
REV. 1.0.2
The XR16L784 has a global interrupt source register
set that consists of 4 consecutive registers [INT0,
INT1, INT2 and INT3]. Register INT3 is not used in
the 784 UART, only in the 8-channel XR16L788. The
3 registers are in the device configuration register ad-
dress space.
All 4 registers default to logic zero (as indicated in
square braces) for no interrupt pending. All 4 channel
interrupts are enabled or disabled in each channel’s
IER register. INT0 shows individual status for each
channel while INT1 and INT2 show the details of the
source of each channel’s interrupt with its unique 3-
bit encoding.
in sequence for clarity. The 16-bit timer and sleep
wake-up interrupts are masked in the device configu-
ration registers,
is generated (if enabed) by the 784 when awakened
from sleep if all 4 channels were placed in the sleep
mode previously.
F
INT3 (Rsvd)
1.1.1 The Global Interrupt Source Registers
IGURE
[0x00]
Bit
2
Reserved
Bit
4. T
1
Bit
HE
0
Figure 4
INT3 Register
G
TIMERCNTL and SLEEP.
Bit
2
[0x00]
LOBAL
INT2
Reserved
Bit
1
shows the 4 interrupt registers
I
Bit
NTERRUPT
0
Bit
2
[0x00]
Reserved
INT1
Bit
1
R
EGISTERS
Bit
0
An interrupt
Bit
2
Reserved
[0x00]
INT0
INT0, INT1, INT2 and INT3
Bit
1
, INT0, INT1, INT2
Interrupt Registers,
INT2 Register
Bit
0
Bit
2
8
Channel-3
Each bit in the INT0 register gives an indication of
the channel that has requested service.
For example, bit-0 represents channel 0 and bit-3 in-
dicates channel 3. Bits 4 to 7 are reserved and re-
mains at logic zero. Logic one indicates the channel
N [3:0] has called for service. The interrupt bit clears
after reading the appropiate register of the interrupt-
ing UART channel register (ISR, LSR and MSR).
See Table 9 for interrupt clearing details.
INT2 and INT1 provide a 12-bit (3 bits per channel)
encoded interrupt indicator. Table 3 shows the 3 bit
encoding and their priority order. The 16-bit Timer
time-out interrupt will show up only as a channel 0 in-
terrupt . For other channels, interrupt 7 is reserved.
.
INT0 C
INT1
Bit
1
R svd
B it-7
Bit
0
AND
HANNEL
AND
R svd
B it-6
In d ivid u a l U A R T C h a n n e l In te rru p t S ta tu s
Bit
2
INT2 I
Channel-2
Rsvd
Bit-7
INT3
Bit
1
R svd
B it-5
I
NTERRUPT
Rsvd
NTERRUPT
Bit-6
Bit
0
IN T0 Register
Rsvd
R svd
Bit-5
B it-4
Bit
2
Channel-1
INT0 Register
Rsvd
Bit-4
INT1 Register
Bit
1
I
C h -3
B it-3
S
NDICATOR
OURCE
Ch-3
Bit-3
Bit
0
B it-2
C h -2
Ch-2 Ch-1 Ch-0
Bit-2
Bit
2
Channel-0
L
:
OCATOR
Bit-1
Bit
1
C h -1
B it-1
Bit-0
Bit
0
C h -0
B it-0