XR16L784 Exar Corporation, XR16L784 Datasheet - Page 11

• Manufacturer Part Number: XR16L784
• Description: High Performance 5V And 3.3V Quad Uart
• Manufacturer: Exar Corporation

TIMER [7:0] (default 0x00): Reserved.
TIMERMSB [7:0] and TIMERLSB [7:0]
TIMERMSB and TIMERLSB form a 16-bit value. The
least-significant bit of the timer is being bit [0] of the
Each bit selects 8X or 16X sampling rate for that
UART channel, bit-0 is channel 0. Logic 0 (default)
selects normal 16X sampling with logic one selects
8X sampling rate. Transmit and receive data rates will
double by selecting 8X.
The 8-bit Reset register [RESET] provides the soft-
ware with the ability to reset individual UART(s) when
there is a need. Each bit is self-resetting after it is
written a logic 1 to perform a reset to that channel. All
1.1.3 8XMODE [7:0] (default 0x00)
1.1.4 REGA [7:0] is reserved
1.1.5 RESET [7:0] (default 0x00)
B it-7 B it-6 B it-5 B it-4 B it-3 B it-2 B it-1 B it-0
R svd
B it-7 B it-6 B it-5 B it-4 B it-3 B it-2 B it-1 B it-0
Individ ual U A R T C hann el 8X C lo ck M ode E nab le
Bit-15
R svd
Individual U A R T C hannel Reset E nable
R svd
R svd
Bit-14
REGA [7:0]
R svd R svd C h-3 C h-2 C h-1 C h-0
R svd R svd C h-3 C h-2 C h-1 C h-0
8XM ODE Register
Bit-13
R ES ET R egister
TIMERMSB Register
(default 0x00)
Bit-12
IS RESERVED
B it-7 B it-6
R s v d
Bit-11
16-Bit Timer/Counter Programmable Registers
(default 0x00)
R s v d
Bit-10
B it-5 B it-4 B it-3 B it-2
R s v d
TIM E R C N TL R egister
Bit-9
R s v d
Bit-8
11
S e le c t
C lo c k
TIMERLSB with most-significant-bit being bit [7] in
TIMERMSB. Reading the TIMERCNTL register will
clear its interrupt. Default value is zero upon pow-
erup and reset.
registers in that channel will be reset to the default
condition, see
0 =1 resets UART channel 0 with bit-3=1 resets
channel 3.
The 8-bit Sleep register enables each UART sepa-
rately to enter Sleep mode. Sleep mode reduces
power consumption when the system needs to put
the UART(s) to idle. The UART enters sleep mode
when there is no interrupt pending. When all 4 UARTs
are put to sleep, the on-chip oscillator shuts off to fur-
ther conserve power. In this case, the quad UART is
awakened by any of the UART channel on from a re-
ceive data byte or a change on the modem port
(CTS#, DSR#, CD# and RI#). The UART is ready af-
ter 32 crystal clocks to ensure full functionality. Also,
a special interrupt is generated with an indication of
no pending interrupt. Logic 0 (default) and logic 1 dis-
able and enable sleep mode respectively.
There are 2 internal registers that provide device
identification and revision, DVID and DREV registers.
The 8-bit content in the DVID register provides device
identification. A return value of 0x24 from this register
HIGH PERFORMANCE 5V AND 3.3V QUAD UART
1.1.6 SLEEP [7:0] (default 0x00)
1.1.7 Device Identification and Revision
Bit-7
R e -trig g e r
B it-7 B it-6 B it-5 B it-4 B it-3 B it-2 B it-1 B it-0
R svd
S in g le /
Bit-6
Individual U AR T C hannel S leep Enable
R svd
B it-1
S ta rt/
S to p
Bit-5
Table 15
R svd R svd C h-3 C h-2 C h-1 C h-0
TIMERLSB Register
B it-0
S LE EP Register
E n a b le
IN T
Bit-4
for details. As an example, bit-
Bit-3
Bit-2
Bit-1
XR16L784
REV. 1.0.1
Bit-0