XR16L784 Exar Corporation, XR16L784 Datasheet - Page 12

• Manufacturer Part Number: XR16L784
• Description: High Performance 5V And 3.3V Quad Uart
• Manufacturer: Exar Corporation

XR16L784
HIGH PERFORMANCE 5V AND 3.3V QUAD UART
REV. 1.0.2
indicates the device is a XR16L784. The DREV regis-
ter returns a 8-bit value of 0x01 for revision A, 0x02
for revision B and so on. This information is very use-
ful to the software driver for identifying which device it
is communicating with and to keep up with revision
changes.
DVID [7:0] default 0x24)
Device identification for the type of UART. The upper
nibble indicates it is a XR16L78x series with lower
nibble indicating the number of channels.
Examples:
XR16L784 = 0x24
XR16L788 = 0x28
DREV [7:0] (default (0x01)
Revision number of the XR16L784. A 0x01 repre-
sents "revision-A" with 0x02 for rev-B and so forth.
REGB register provides a control for simultaneous
write to all 4 UARTs configuration registers or individ-
ually. This is very useful for device intialization in the
power up and reset routines.
The 784 includes an on-chip oscillator (XTAL1 and
XTAL2). The crystal oscillator provides the system
clock to the Baud Rate Generators (BRG) in each of
the 4 UARTs, the 16-bit general purpose timer/
counter and internal logics. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin
being the output. For programming details, see “Pro-
grammable Baud Rate Generator” on page 13 .
The on-chip oscillator is designed to use an industry
standard microprocessor crystal (parallel resonant
with 10-22 pF capacitance load, 100ppm) connected
REGB[0]
REGB[7:1]
2.0 CRYSTAL OSCILLATOR / BUFFER
1.1.8 REGB [7:0] (default 0x00)
Logic 0 (default) write to each UART
configuration registers individually.
Logic 1 enables simultaneous write to
all 4 UARTs configuration register. Use-
ful during device initialization.
Reserved
12
F
externally between the XTAL1 and XTAL2 pins (see
Figure 6
nected to the XTAL1 pin to clock the 4 internal baud
rate generators for standard or custom rates. Typical
oscillator connections are shown in Figure 6. For fur-
ther reading on oscillator circuit please see applica-
tion note DAN108 on EXAR’s web site.
Each UART channel has a transmit holding register
(THR) and a receive holding register (RHR). The
THR and RHR registers are 16550 compatible so
their access is limited to 8-bit format. The software
driver must separately read the LSR content for the
associated error flags before reading the data byte.
The THR and RHR register addresses for channel 0
to channel 3 is shown in
RHR for channels 0 to 3 are located at address 0x00,
0x10, 0x20 and 0x30 respectively. Transmit data byte
is loaded to the THR when writting to that address
and receive data is unloaded from the RHR register
when reading from that address. Both THR and RHR
registers are 16C550 compatible in 8-bit format, so
each bus operation can only write or read in bytes.
3.0 TRANSMIT AND RECEIVE DATA
3.1 FIFO DATA LOADING AND UNLOADING
IGURE
THROUGH THE UART CHANNEL REGIS-
TERS, THR AND RHR.
). Alternatively, an external clock can be con-
6. T
YPICAL OSCILLATOR CONNECTIONS
2 2-4 7 pF
X T A L 1
C 1
R =3 0 0 K to 40 0 K
1 4.7 45 6
M H z
Table 5
2 2-4 7 pF
below. The THR and
X T A L 2
C 2