XR16L784 Exar Corporation, XR16L784 Datasheet - Page 13

• Manufacturer Part Number: XR16L784
• Description: High Performance 5V And 3.3V Quad Uart
• Manufacturer: Exar Corporation

.
There are 4 UARTs [channel 3:0] in the 784. Each
has its own 64-byte of transmit and receive FIFO, a
set of 16550 compatible control and status registers,
and a baud rate generator for individual channel data
rate setting. Eight additional registers per UART were
added for the EXAR enhanced features.
Each UART has its own Baud Rate Generator (BRG)
with a prescaler for the transmiter and receiver. The
prescaler is controlled by a software bit in the MCR
Programming the Baud Rate Generator Registers
DLM and DLL provides the capability of selecting the
operating data rate.
4.0 UART
4.1 P
ROGRAMMABLE
F
IGURE
XTAL1
XTAL2
C H 0 0x00 W rite T H R
C H 0 0x00 R ead R H R
C H 1 0x10 W rite T H R
C H 2 0x20 W rite T H R
C H 3 0x30 W rite T H R
C H 1 0x10 R ead R H R
C H 2 0x20 R ead R H R
C H 3 0x30 R ead R H R
T
Table 6
7. B
ABLE
B
TH R and RH R Address Locations For CH 0 to CH 3 (16C 550 Com patible)
AUD
AUD
5: T
shows the standard data
R
R
RANSMIT AND
ATE
Crystal
Buffer
Osc/
ATE
G
G
ENERATOR
Channels
To Other
ENERATOR
B it-7
B it-7
B it-7
B it-7
B it-7
B it-7
B it-7
B it-7
R
Divide by 4
ECEIVE
Divide by 1
Prescaler
Prescaler
B it-6
B it-6
B it-6
B it-6
B it-6
B it-6
B it-6
B it-6
D
13
ATA
B it-5
B it-5
B it-5
B it-5
B it-5
B it-5
B it-5
B it-5
register. The MCR register bit-7 sets the prescaler to
divide the input crystal or external clock by 1 or 4.
The output of the prescaler clocks to the BRG. The
BRG further divides this clock by a programmable di-
visor between 1 and (2
sampling clock of the serial data rate. The sampling
clock is used by the transmitter for data bit shifting
and receiver for data sampling. The BRG divisor (DLL
and DLM registers) defaults to a random value upon
power up. Therefore, the BRG must be programmed
during initialization to the operating data rate.
rates available with a 14.7456 MHz crystal or external
clock at 16X clock rate. At 8X sampling rate, these
data rates would double. When using a non-standard
HIGH PERFORMANCE 5V AND 3.3V QUAD UART
MCR Bit-7=0
MCR Bit-7=1
R
(default)
EGISTER
B it-4
B it-4
B it-4
B it-4
B it-4
B it-4
B it-4
B it-4
Baud Rate
DLL and DLM
Generator
B it-3
B it-3
B it-3
B it-3
B it-3
B it-3
B it-3
B it-3
Registers
Logic
, 16C550
B it-2
B it-2
B it-2
B it-2
B it-2
B it-2
B it-2
B it-2
COMPATIBLE
16
B it-1
B it-1
B it-1
B it-1
B it-1
B it-1
B it-1
B it-1
Rate Clock to
and Receiver
Transmitter
-1) to obtain a 16X or 8X
16X or 8X
Sampling
784TH R R H R 1
B it-0
B it-0
B it-0
B it-0
B it-0
B it-0
B it-0
B it-0
XR16L784
REV. 1.0.1