XR16L784 Exar Corporation, XR16L784 Datasheet - Page 14

• Manufacturer Part Number: XR16L784
• Description: High Performance 5V And 3.3V Quad Uart
• Manufacturer: Exar Corporation

XR16L784
HIGH PERFORMANCE 5V AND 3.3V QUAD UART
REV. 1.0.2
data rate crystal or external clock, the divisor value
can be calculated for channel ‘N’ with the following
equation(s).
Automatic RTS/DTR flow control is used to prevent
data overrun to the local receiver FIFO. The RTS#/
DTR# output pin is used to request remote unit to
suspend/resume data transmission. The flow control
features are individually selected to fit specific appli-
cation requirement (see Figure 8):
• Select RTS (and CTS) or DTR (and DSR) through
• Enable auto RTS/DTR flow control using EFR bit-6.
• The auto RTS/DTR function must be started by
• Enable RTS/DTR interrupt through IER bit-6 (after
• Select Hysteresis values when used with program-
O
4.2 A
MCR bit-2.
asserting RTS/DTR# output pin (MCR bit-0 or 1 to
logic 1 after it is enabled.
setting EFR bit-4). The UART issues an interrupt
when the RTS#/DTR# pin makes a transition: ISR
bit-5 will be set to 1.
mable RX FIFO trigger levels.
UTPUT
MCR Bit-7=1
T
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16),
divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 8),
230.4k
TROL
115.2k
19.2k
38.4k
57.6k
ABLE
1200
2400
4800
9600
100
600
UTOMATIC
Data Rate
O
6: T
PERATION
YPICAL DATA RATES WITH A
RTS/DTR H
O
UTPUT
MCR Bit-7=0
153.6k
230.4k
460.8k
921.6k
19.2k
38.4k
76.8k
2400
4800
9600
400
Data Rate
ARDWARE
Clock (Decimal)
D
IVISOR FOR
F
LOW
2304
14.7456 MH
384
192
96
48
24
12
6
4
2
1
C
ON
16x
-
D
14
IVISOR FOR
Z CRYSTAL OR EXTERNAL CLOCK AT
Clock (HEX)
• Automatic CTS/DSR flow control is used to prevent
• Select CTS (and RTS) or DSR (and DTR) through
• Enable auto CTS/DSR flow control using EFR bit-
• Enable CTS/DSR interrupt through IER bit-7 (after
4.2.1 Automatic CTS/DSR Hardware Flow Con-
data overrun to the remote receiver FIFO. The
CTS/DSR pin is monitored to suspend/restart local
transmitter. The flow control features are individu-
ally selected to fit specific application requirement
(see Figure 8):
CR bit-2.
7.
setting EFR bit-4). The UART issues an interrupt
when the CTS#/DSR# pin makes a transition: ISR
bit-5 will be set to 1, and UART will suspend TX
transmissions as soon as the stop bit of the charac-
ter in process is shifted out. Transmission is
resumed after the CTS#/DSR# input returns to
logic 0, indicating more data may be sent.
900
180
C0
0C
60
30
18
06
04
02
01
16x
trol Operation
DLM P
V
ALUE
09
01
00
00
00
00
00
00
00
00
00
ROGRAM
(HEX)
WHEN
WHEN
8XMODE-
8XMODE-
DLL P
V
ALUE
C0
0C
00
80
60
30
18
06
04
02
01
16X S
ROGRAM
(HEX)
BIT
BIT
N
N
AMPLING
IS
IS
D
E
0
1
ATA
RROR
0
0
0
0
0
0
0
0
0
0
0
R
ATE
(%)