XR16L784 Exar Corporation, XR16L784 Datasheet - Page 28

• Manufacturer Part Number: XR16L784
• Description: High Performance 5V And 3.3V Quad Uart
• Manufacturer: Exar Corporation

XR16L784
HIGH PERFORMANCE 5V AND 3.3V QUAD UART
REV. 1.0.2
goes idle. It is set to logic 0 whenever either the THR
or TSR contains a data character. In the FIFO mode
this bit is set to one whenever the transmit FIFO and
transmit shift register are both empty.
LSR[7]: Receive FIFO Data Error Flag
• Logic 0 = No FIFO error. (default)
• Logic 1 = An indicator for the sum of all error bits in
This register provides the current state of the modem
interface signals, or other peripheral device that the
UART is connected. Lower four bits of this register
are used to indicate the changed information. These
bits are set to a logic 1 whenever a signal from the
modem changes state. These bits may be used as
general purpose inputs/outpus when they are not
used with modem signals.
MSR[0]: Delta CTS# Input Flag
• Logic 0 = No change on CTS# input (default).
• Logic 1 = The CTS# input has changed state since
MSR[1]: Delta DSR# Input Flag
• Logic 0 = No change on DSR# input (default).
• Logic 1 = The DSR# input has changed state since
MSR[2]: Delta RI# Input Flag
• Logic 0 = No change on RI# input (default).
• Logic 1 = The RI# input has changed from a logic 0
MSR[3]: Delta CD# Input Flag
• Logic 0 = No change on CD# input (default).
• Logic 1 = Indicates that the CD# input has changed
MSR[4]: CTS Input Status
Only
4.11.7 Modem Status Register (MSR) - Read
the RX FIFO. At least one parity error, framing error
or break indication is in the FIFO data. This bit
clears when there is no more error(s) in the FIFO.
the last time it was monitored. A modem status
interrupt will be generated if MSR interrupt is
enabled (IER bit-3.
the last time it was monitored. A modem status
interrupt will be generated if MSR interrupt is
enabled (IER bit-3.
to a logic 1, ending of the ringing signal. A modem
status interrupt will be generated if MSR interrupt is
enabled (IER bit-3.
state since the last time it was monitored. A modem
status interrupt will be generated if MSR interrupt is
enabled (IER bit-3.
28
CTS# pin may function as automatic hardware flow
control signal input if it is enabled and selected by Au-
to CTS (EFR bit-7) and RTS/CTS flow control select
(MCR bit-2). Auto CTS flow control allows starting
and stopping of local data transmissions based on
the modem CTS# signal. A logic 1 on the CTS# pin
will stop UART transmitter as soon as the current
character has finished transmission, and a logic 0 will
resume data transmission. Normally MSR bit-4 bit is
the compliment of the CTS# input. However in the
loopback mode, this bit is equivalent to the RTS# bit
in the MCR register. The CTS# input may be used as
a general purpose input when the modem interface is
not used.
MSR[5]: DSR Input Status
DSR# (active high, logical 1). This input may be used
for auto DTR/DSR flow control function, see auto
\hardware flow control section. Normally this bit is the
compliment of the DSR# input. In the loopback mode,
this bit is equivalent to the DTR# bit in the MCR regis-
ter. The DSR# input may be used as a general pur-
pose input when the modem interface is not used.
MSR[6]: RI Input Status
RI# (active high, logical 1). Normally this bit is the
compliment of the RI# input. In the loopback mode
this bit is equivalent to bit-2 in the MCR register. The
RI# input may be used as a general purpose input
when the modem interface is not used.
MSR[7]: CD Input Status
CD# (active high, logical 1). Normally this bit is the
compliment of the CD# input. In the loopback mode
this bit is equivalent to bit-3 in the MCR register. The
CD# input may be used as a general purpose input
when the modem interface is not used.
The upper four bits 4-7 of this register sets the delay
in number of bits time for the auto RS485 turn around
from transmit to receive.
MSR [7:4]
When Auto RS485 feature is enabled (FCTR bit-5=1)
and RTS# output is connected to the enable input of
a RS-485 transceiver. These 4 bits select from 0 to 15
bit-time delay after the end of the last stop-bit of the
last transmitted character. This delay controls when
to change the state of RTS# output. This delay is
very useful in long-cable networks. Table 12 shows
the selection. The bits are enabled by EFR bit-4.
Only
4.11.8 Modem Status Register (MSR) - Write