XR16L784 Exar Corporation, XR16L784 Datasheet - Page 42

• Manufacturer Part Number: XR16L784
• Description: High Performance 5V And 3.3V Quad Uart
• Manufacturer: Exar Corporation

XR16L784
HIGH PERFORMANCE 5V AND 3.3V QUAD UART
REV. P1.0.2
GENERAL DESCRIPTION ............................................................................................... 1
PIN DESCRIPTIONS ....................................................................................................... 3
DESCRIPTION .................................................................................................................. 6
1.0 XR16L784 REGISTERS ......................................................................................................................... 6
1.1
2.0 CRYSTAL OSCILLATOR / BUFFER .................................................................................................... 12
3.0 TRANSMIT AND RECEIVE DATA ........................................................................................................ 12
3.1 FIFO DATA LOADING AND UNLOADING THROUGH THE UART CHANNEL REGISTERS, THR AND RHR. ..... 12
4.0 UART ..................................................................................................................................................... 13
4.1 P
4.2 A
4.3 I
4.4 I
4.5 UART CHANNEL CONFIGURATION REGISTERS AND ADDRESS DECODING. ................................................. 17
4.6 T
DEVICE CONFIGURATION REGISTER SET .......................................................................................... 6
A
NEW F
Figure 1. Block Diagram ....................................................................................................................... 1
Figure 2. Pin Out Assignment .............................................................................................................. 2
ORDERING INFORMATION
Figure 3. The XR16L784 Registers Mapping ....................................................................................... 6
T
T
Figure 4. The Global Interrupt Registers, INT0, INT1, INT2 and INT3 ............................................... 8
T
Figure 5. Timer/Counter circuit. ........................................................................................................... 9
T
Figure 6. Typical oscillator connections ........................................................................................... 12
T
Figure 7. Baud Rate Generator ........................................................................................................... 13
T
Figure 8. Auto RTS/DTR and CTS/DSR Flow Control Operation ..................................................... 15
NFRARED
Figure 9. Infrared Transmit Data Encoding and Receive Data Decoding ....................................... 16
NTERNAL
Figure 10. Internal Loop Back ............................................................................................................ 17
T
T
Figure 11. Transmitter Operation in non-FIFO Mode ....................................................................... 20
ROGRAMMABLE
UTOMATIC
RANSMITTER
PPLICATIONS
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
ABLE
1.1.1 The Global Interrupt Source Registers ..................................................................................... 8
1.1.2 General Purpose 16-bit Timer/Counter. [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (default
0xXX-XX-00-00) ................................................................................................................................ 9
1.1.3 8XMODE [7:0] (default 0x00) ................................................................................................ 11
1.1.4 REGA [7:0] is reserved (default 0x00) .................................................................................. 11
1.1.5 RESET [7:0] (default 0x00) .................................................................................................... 11
1.1.6 SLEEP [7:0] .....................................................................................................(default 0x00) 11
1.1.7 Device Identification and Revision ......................................................................................... 11
1.1.8 REGB [7:0] ......................................................................................................(default 0x00) 12
4.2.1 Automatic CTS/DSR Hardware Flow Control Operation ........................................................ 14
4.6.1 Transmit Holding Register (THR) ........................................................................................... 20
4.6.2 Transmitter Operation in non-FIFO ........................................................................................ 20
4.6.3 Transmitter Operation in FIFO ............................................................................................... 20
INT0 Channel Interrupt Indicator: ...................................................................................................................... 8
INT1 and INT2 Interrupt Source Locator ........................................................................................................... 8
1: XR16L784 R
2: D
3: UART C
4: TIMER CONTROL R
5: T
6: T
7: UART CHANNEL CONFIGURATION REGISTERS. ............................................................. 18
8: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. S
EATURES
L
M
OOPBACK
RTS/DTR H
BY
ODE
RANSMIT AND
YPICAL DATA RATES WITH A
EVICE
............................................................................................................................................................. 20
EFR B
B
......................................................................................................................................................... 15
........................................................................................................................................... 1
AUD
....................................................................................................................................... 1
C
HANNEL
.................................................................................................................................................. 16
ONFIGURATION
R
IT
ARDWARE
ATE
-4. ........................................................................................................................ 19
EGISTER
............................................................................................................................ 2
R
G
ECEIVE
[3:0] I
ENERATOR
F
EGISTER
LOW
S
NTERRUPT
ETS
D
R
TABLE OF CONTENTS
ATA
C
EGISTERS
.................................................................................................................. 13
ONTROL
....................................................................................................... 7
14.7456 MH
R
................................................................................................. 10
EGISTER
S
O
OURCE
.......................................................................................... 7
PERATION
, 16C550
Z CRYSTAL OR EXTERNAL CLOCK AT
I
E
NCODING AND
.................................................................................. 14
COMPATIBLE
C
LEARING
.............................................. 13
....................................... 9
HADED BITS ARE ENABLED
PRELIMINARY
16X S
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AMPLING
. 14