XR16L784 Exar Corporation, XR16L784 Datasheet - Page 26

• Manufacturer Part Number: XR16L784
• Description: High Performance 5V And 3.3V Quad Uart
• Manufacturer: Exar Corporation

XR16L784
HIGH PERFORMANCE 5V AND 3.3V QUAD UART
REV. 1.0.2
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in con-
junction with the programmed word length.
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The
parity bit is a simple way used in communications for
data integrity check. See
summary below.
• Logic 0 = No parity.
• Logic 1 = A parity bit is generated during the trans-
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic
1, LCR BIT-4 selects the even or odd parity format.
Logic 0 = ODD Parity is generated by forcing an odd
number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same for-
mat. (default).
• Logic 1 = EVEN Parity is generated by forcing an
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR BIT-5 selects the
forced parity format.
• LCR BIT-5 = logic 0, parity is not forced. (default)
• LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity
mission while the receiver checks for parity error of
the data character received.
even the number of logic 1’s in the transmitted
character. The receiver must be programmed to
check the same format.
bit is forced to a logical 1 for the transmit and
receive data.
BIT-1
BIT-2
0
0
1
1
0
1
1
W
ORD LENGTH
BIT-0
5,6,7,8
6,7,8
0
1
0
1
5
Table 11
S
W
for parity selection
TOP BIT LENGTH
(B
5 (default)
ORD LENGTH
1 (default)
IT TIME
1-1/2
6
7
8
2
(
S
))
26
• LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity
LCR[6]: Transmit Break Enable
• When enabled the Break control bit it causes a
• Logic 0 = No TX break condition. (default)
• Logic 1 = Forces the transmitter output (TX) to a
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL/DLM) enable.
• Logic 0 = Data registers are selected. (default)
• Logic 1 = Divisor latch registers are selected.
This register controls the serial interface signals with
the modem or a peripheral device.
Modem Control Register (MCR)
The MCR register is used for controlling the modem
interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Pins
The DTR# pin may be used for automatic hardware
flow control enabled by EFR bit-6 and MCR bit-2=1. If
the modem interface is not used, this output may be
used for general purpose.
• Logic 0 = Force DTR# output to a logic 1. (default)
• Logic 1 = Force DTR# output to a logic 0.
MCR[1]: RTS# Pins
The RTS# pin may be used for automatic hardware
flow control by enabled by EFR bit-6 and MCR bit-
2=0. If the modem interface is not used, this output
may be used for general purpose.
• Logic 0 = Force RTS# output to a logic 1. (default)
eral Purpose Outputs Control.
LCR B
4.11.5 Modem Control Register (MCR) or Gen-
bit is forced to a logical 0 for the transmit and
receive data.
break condition to be transmitted (the TX output is
forced to a “space’, logic 0, state). This condition
remains until disabled by setting LCR bit-6 to a
logic 0.
“space”, logic 0, for alerting the remote receiver of
a line break condition.
X
0
0
1
1
IT
-5 LCR B
T
ABLE
X
0
1
0
1
IT
-4 LCR B
11: P
ARITY SELECTION
0
1
1
1
1
IT
-3
Force parity to mark, “1”
Forced parity to space,
P
ARITY SELECTION
Even parity
Odd parity
No parity
“0”