XR16L784 Exar Corporation, XR16L784 Datasheet - Page 19

• Manufacturer Part Number: XR16L784
• Description: High Performance 5V And 3.3V Quad Uart
• Manufacturer: Exar Corporation

N
available in the XR16L784. They are present for 16C550
compatibility during Internal loopback, see Figure 10.
A
OTE
T
A3-A0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 1
0 0 0 1
0 0 1 0
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 0
1 0 1 1
1 0 1 1
1 1 0 0
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
DDRESS
ABLE
2: MCR bits 2 and 3 (OP1 and OP2 outputs) are not
8: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION.
RFCNT
XCHAR
TFCNT
TFTRG
RFTRG
XOFF1
XOFF2
N
FCTR
XON1
XON2
MCR
MSR
MSR
R
RHR
THR
DLM
FCR
SPR
LCR
LSR
EFR
DLL
IER
ISR
AME
EG
W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EAD
RITE
W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
/
CTS/DSR#
Int. Enable
BRG Pres-
TRG Table
Auto CTS/
RX FIFO
RX FIFO
Trigger
Enable
Divisor
Enable
E
RS485
Enable
FIFOs
DLY-3
B
caler
DSR
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
RROR
Bit-1
CD
IT
0/
0/
0/
0/
0/
-7
RTS/DTR#
Int. Enable
TRG Table
Auto RTS/
RX FIFO
Enable
Trigger
Set TX
Enable
RS485
Enable
FIFOs
Empty
DLY-2
B
Break
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
DTR
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
TSR
Bit-0
IT
IR
RI
0/
0/
0/
0/
0/
-6
Int. Enable
DeltaFlow
Set Parity Even Par-
Sp. Char.
Xon/Xoff/
TX FIFO
XonAny
Special
Trigger
Enable
RS485
RS485
Empty
DLY-1
Select
B
Bit-5
Bit-5
Bit-5
Bit-5
THR
DSR
Bit-5
Auto
Char
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Cntl
IT
0/
0/
0/
0/
0/
-5
19
RX Break RX Fram-
IER [7:4],
ISR [5:4],
FCR[5:4],
MCR[7:5]
MSR[7:4]
Xoff/spe-
RX Input
cial char
TX FIFO
Lopback
Invert IR
Internal
Trigger
Enable
RS485
Enable
DLY-0
B
Bit-4
Bit-4
Bit-4
Bit-4
CTS
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
HIGH PERFORMANCE 5V AND 3.3V QUAD UART
IT
ity
0/
0/
0/
0
-4
INT Source
DMA Mode TX FIFO
Delta CD#
Status Int.
Reserved Reserved Reserved Reserved
RTS/DTR
Hyst Bit-3
Flow Cntl
Software
ing Error
Modem
Enable
Enable
B
Parity
OP2
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
IT
-3
2
INT Source
Status Int.
RTS/DTR
RTS/DTR
Hyst Bit-2
RX Parity
Flow Cntl
Stop Bits
Software
Flow Sel
RX Line
Enable
OP1
B
Reset
Error
Delta
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
RI#
IT
-2
2
/
S
HADED BITS ARE ENABLED BY
INT Source
Int. Enable
TX Empty
Hyst Bit-1
RTS# Pin
RTS/DTR
RX Over-
Flow Cntl
RX FIFO
Software
Xon Det.
Indicator
Control
Length
B
Reset
DSR#
Word
Delta
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
run
IT
-1
INT Source
Int. Enable
DTR# Pin
RTS/DTR
Hyst Bit-0
Flow Cntl
Software
RX Data
RX Data
Xoff Det.
Indicator
Control
Enable
Length
Ready
FIFOs
B
CTS#
Word
Delta
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
IT
-0
XR16L784
REV. 1.0.1
EFR B
C
User Data
LCR[7]=0
after read
LCR[7]=0
LCR[7]=1
LCR[7]=1
Self-clear
OMMENT
IT
-4.