XR16L784 Exar Corporation, XR16L784 Datasheet - Page 22

• Manufacturer Part Number: XR16L784
• Description: High Performance 5V And 3.3V Quad Uart
• Manufacturer: Exar Corporation

XR16L784
HIGH PERFORMANCE 5V AND 3.3V QUAD UART
REV. 1.0.2
The Interrupt Enable Register (IER) masks the inter-
rupts from receive data ready, transmit empty, line
status and modem status registers. These interrupts
are reported in the Interrupt Status Register (ISR)
register and also encoded in INT (INT0-INT3) register
in the Device Configuration Registers.
When the receive FIFO (FCR BIT-0 = a logic 1) and
receive interrupts (IER BIT-0 = logic 1) are enabled,
F
F
4.9 IER
4.8.3 Interrupt Enable Register (IER)
IGURE
IGURE
(8 X M O D E R e g is te r)
O
Receive Data
Byte and Errors
a n d E rro rs
16X or 8X Sampling
Clock (8XMODE Reg.)
D a ta B y te
PERATION
13. R
14. R
1 6 X o r 8 X C lo c k
R e c e iv e
VERSUS
64 bytes by 11-
bit wide FIFO
ECEIVER
ECEIVER
R
ECEIVE
O
O
PERATION IN NON
PERATION IN
FIFO I
LS R bits
F la g s in
Receive Data Shift
E rror
3:1
Register (RSR)
NTERRUPT
Receive Data
Receive
R e c e iv e D a ta S h ift
(64-byte)
FIFO
FIFO
Data
R e g is te r (R S R )
H o ld in g R e g is te r
-FIFO M
R e c e iv e D a ta
AND
M
(R H R )
ODE
F
Data falls to 40
FIFO Trigger=48
Data fills to 56
Validation
LOW
Data Bit
ODE
Example:
- FIFO trigger level set at 48 bytes
- RTS/DTR hyasteresis set at +/-8 chars.
C
22
ONTROL
the RHR interrupts (see ISR bits 3 and 4) status will
reflect the following:
A. The receive data available interrupts are issued
B. FIFO level will be reflected in the ISR register
RTS#/DTR# re-asserts when data falls below the
trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
RTS#/DTR# de-asserts when data fills above
the trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
V a lid a tio n
to the host when the FIFO has reached the pro-
grammed trigger level. It will be cleared when the
FIFO drops below the programmed trigger level.
when the FIFO trigger level is reached. Both the
ISR register status bit and the interrupt will be
cleared when the FIFO drops below the trigger
level.
RHR Interrupt (ISR bit-2) is programmed at
FIFO trigger level (RXTRG).
FIFO is Enable by FCR bit-0=1
D a ta B it
M
ODE
R H R In te rru p t (IS R b it-2 )
Receive Data Characters
R e c e iv e D a ta C h a ra c te rs
R X F IF O 1
RXFIFO1