XR16L784 Exar Corporation, XR16L784 Datasheet - Page 30

• Manufacturer Part Number: XR16L784
• Description: High Performance 5V And 3.3V Quad Uart
• Manufacturer: Exar Corporation

XR16L784
HIGH PERFORMANCE 5V AND 3.3V QUAD UART
REV. 1.0.2
FCTR[4]: Infrared RX Input Logic Select
0 = Select RX input as active high encoded IrDA da-
ta, normal, (default).
1 = Select RX input as active low encoded IrDA data,
inverted.
FCTR[5]: Auto RS485 Enable
Auto RS485 half duplex control enable/disable.
• 0 = Standard ST16C550 mode. Transmitter gener-
• 1 = Enable Auto RS485 half duplex direction con-
FCTR[7:6]: TX and RX FIFO Trigger Table Select
ates an interrupt when transmit holding register
(THR) becomes empty. Transmit Shift Register
(TSR) may still be shifting data bit out.
trol. RTS# output changes its logic level from 1 to 0
when finished sending the last stop bit of the last
character out of the TSR register. It changes back
to logic level 1 from 0 when a data byte is loaded
into the THR or transmit FIFO. The change to logic
1 occurs prior sending the start-bit. It also changes
the transmitter interrupt from transmit holding to
transmit shift register (TSR) empty.
T
ABLE
FCTR B
13: 16 S
3
0
0
1
1
1
1
1
1
1
1
IT
-
ELECTABLE
FCTR B
2
1
1
1
1
1
1
0
0
0
0
IT
H
-
YSTERESIS
FCTR B
1
1
1
0
0
1
1
0
0
1
1
IT
-
L
EVELS
30
FCTR B
These 2 bits select the transmit and receive FIFO trig-
ger level table A, B, C or D. When table A, B, or C is
selected the auto RTS flow control trigger level is set
to "next FIFO trigger level" for compatibility to
ST16C550 and ST16C650 series. RTS/DTR# trig-
gers on the next level of the RX FIFO trigger level, in
other words, one FIFO level above and one FIFO lev-
el below. See
FCR bit 4-5 and FCTR bit 6-7. For example, if Table C
is used on the receiver with RX FIFO trigger level set
to 56 bytes, RTS/DTR# output will de-assert at 60
and re-assert at 16.
Enhanced features are enabled or disabled using this
register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see
Table 14). When the Xon1 and Xon2 and Xoff1 and
Xoff2 modes are selected, the double 8-bit words are
concatenated into two sequential characters. Cau-
tion: note that whenever changing the TX or RX flow
control bits, always reset all bits back to logic 0 (dis-
able) before programming a new setting.
4.11.11 Enhanced Feature Register (EFR)
0
0
1
0
1
0
1
0
1
0
1
W
HEN
IT
-
T
RIGGER
RTS/DTR H
Table 10
(
CHARACTERS
T
ABLE
+/- 24
+/- 32
+/- 12
+/- 20
+/- 28
+/- 36
+/- 40
+/- 44
+/- 48
+/- 52
for complete selection with
YSTERESIS
-D
IS
)
S
ELECTED