IDT82V2048 Integrated Device Technology, Inc., IDT82V2048 Datasheet - Page 43

• Manufacturer Part Number: IDT82V2048
• Manufacturer: Integrated Device Technology, Inc.

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
TABLE - 20. TAP CONTROLLER STATE DESCRIPTION
Select-DR-Scan
Select-IR-Scan
Run-Test/Idle
Capture-DR
Update-DR
Capture-IR
Test Logic
Pause-DR
Exit1-DR
Exit2-DR
Shift-DR
STATE
Shift-IR
Reset
instruction register with the IDCODE instruction.
held high for at least 5 rising edges of TCK. The controller remains in this state while TMS is high. The device processor
automatically enters this state at power-up.
held low. The instruction register and all test data registers retain their previous state. When TMS is high and a rising edge is
applied to TCK, the controller moves to the Select-DR state.
current instruction retains its previous state. If TMS is held low and a rising edge is applied to TCK when in this state, the
controller moves into the Capture-DR state and a scan sequence for the selected test data register is initiated. If TMS is held
high and a rising edge applied to TCK, the controller moves to the Select-IR-Scan state.
SAMPLE/PRELOAD. The instruction does not change in this state. The other test data registers, which do not have parallel
input, are not changed. When the TAP controller is in this state and a rising edge is applied to TCK, the controller enters the
Exit1-DR state if TMS is high or the Shift-DR state if TMS is low.
data on stage toward its serial output on each rising edge of TCK. The instruction does not change in this state. When the
TAP controller is in this state and a rising edge is applied to TCK, the controller enters the Exit1-DR state if TMS is high or
remains in the Shift-DR state if TMS is low.
enter the Update-DR state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK,
the controller enters the Pause-DR state. The test data register selected by the current instruction retains its previous value
and the instruction does not change during this state.
path between TDI and TDO. For example, this state could be used to allow the tester to reload its pin memory from disk
during application of a long test sequence. The test data register selected by the current instruction retains its previous value
and the instruction does not change during this state. The controller remains in this state as long as TMS is low. When TMS
goes high and a rising edge is applied to TCK, the controller moves to the Exit2-DR state.
enter the Update-DR state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK,
the controller enters the Shift-DR state. The test data register selected by the current instruction retains its previous value and
the instruction does not change during this state.
to the EXTEST and SAMPLE/PRELOAD instructions. When the TAP controller is in this state and the Boundary Scan
Register is selected, data is latched into the parallel output of this register from the shift-register path on the falling edge of
TCK. The data held at the latched parallel output changes only in this state. All shift-register stages in the test data register
selected by the current instruction retain their previous value and the instruction does not change during this state.
TMS is held low and a rising edge is applied to TCK when in this state, the controller moves into the Capture-IR state, and a
scan sequence for the instruction register is initiated. If TMS is held high and a rising edge is applied to TCK, the controller
moves to the Test-Logic-Reset state. The instruction does not change during this state.
of TCK. This supports fault-isolation of the board-level serial test data path. Data registers selected by the current instruction
retain their value and the instruction does not change during this state. When the controller is in this state and a rising edge is
applied to TCK, the controller enters the Exit1-IR state if TMS is held high, or the Shift-IR state if TMS is held low.
stage towards its serial output on each rising edge of TCK. The test data register selected by the current instruction retains its
previous value and the instruction does not change during this state. When the controller is in this state and a rising edge is
applied to TCK, the controller enters the Exit1-IR state if TMS is held high, or remains in the Shift-IR state if TMS is held low.
In this state, the Boundary Scan Register captures input pin data if the current instruction is EXTEST or
This is a controller state between scan operations. Once in this state, the controller remains in the state as long as TMS is
This is a temporary controller state and the instruction does not change in this state. The test data register selected by the
The Boundary Scan Register is provided with a latched parallel output to prevent changes while data is shifted in response
In this controller state, the shift register contained in the instruction register loads a fixed value of ‘100’ on the rising edge
In this state, the test logic is disabled. The device is set to normal operation. During initialization, the device initializes the
The pause state allows the test controller to temporarily halt the shifting of data through the test data register in the serial
In this state, the shift register contained in the instruction register is connected between TDI and TDO and shifts data one
Regardless of the original state of the controller, the controller enters the Test-Logic-Reset state when the TMS input is
In this controller state, the test data register connected between TDI and TDO as a result of the current instruction shifts
This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to
This is a temporary controller state. The test data register selected by the current instruction retains its previous state. If
This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to
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DESCRIPTION
INDUSTRIAL TEMPERATURE RANGES