IDT82V2048 Integrated Device Technology, Inc., IDT82V2048 Datasheet - Page 18

• Manufacturer Part Number: IDT82V2048
• Manufacturer: Integrated Device Technology, Inc.

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
which is 16XMCLK as clock reference. This function will be bypassed
when MCLK is unavailable.
TABLE - 7. BUILT-IN WAVEFORM TEMPLATE SELECTION
NOTE:
1. Maximum cable loss at 772 KHz
The built-in waveform shaper use an internal high frequency clock
-0.2
-0.4
-0.6
0.00
-0.20
0.80
1.00
0.60
0.40
0.20
1.2
0.8
0.6
0.4
0.2
1.20
1
0
0
-300
Figure - 10. DSX-1 Waveform Template
Figure - 11. CEPT Waveform Template
TS2
0
0
0
0
1
1
1
1
-200
250
TS1
0
0
1
1
0
0
1
1
-100
500
Time (ns)
Time (ns)
TS0
0
0
1
0
1
0
1
0
1
750
100
Service
E1
T1
1000
200
Clock Rate
2.048 MHz
1.544
300
MHz
1250
18
120
133
266
399
533
Bipolar Violation Insertion
pin TDNn/BPVIn is used as BPVI input. A low-to-high transition on this
pin inserts a bipolar violation on the next available mark in the transmit
data stream. Sampling occurs on the falling edge of TCLK. But in TAOS
with analog loopback mode, remote loopback mode and inband
loopback mode, the BPVI is disabled. In TAOS with digital loopback
mode, the BPVI is looped back to system side, so the data to be trans-
mitted on TTINGn and TRINGn are all ones with no bipolar violation.
JITTER ATTENUATOR
and can be selected to work either in transmit path or in receive path or
not used. The selection is accomplished by setting pin JAS in hardware
mode or configuring bits JACF1 and JACF0 in register GCF in host
mode which are both effected to all eight channels.
need to be extracted for the internal synchronization, the jitter attenuator
is set in the receive path. Another use of the jitter attenuator is to pro-
vide clock smoothing in the transmit path for applications such as syn-
chronous/asynchronous demultiplexing applications. In these applica-
tions, TCLK will have an instantaneous frequency that is higher than the
nominal T1/E1 data rate and in order to set the average long-term TCLK
frequency within the transmit line rate specifications, periods of TCLK
are suppressed (gapped).
gapped TCLK. In host mode, the FIFO length can be 32 X 2 or 64 X 2
bits by programming bit JADP in GCF. In hardware mode, it is fixed to
64 X 2 bits. The FIFO length determines the maximum permissible gap
width (see table-8), exceeding these values will cause FIFO overflow or
underflow. The data is 16 or 32 bits’ delay through the jitter attenuator in
the corresponding transmit or receive path. The constant delay feature
is crucial for the applications requiring “hitless” switching.
corner frequency (fc) for both T1 and E1. In hardware mode, the fc is
fixed to 2.5Hz for T1 or 1.7Hz for E1. Generally, the lower the fc is, the
higher the attenuation. However, lower fc comes at the expense of
increased acquisition time. Therefore, the optimum fc is to optimize both
the attenuation and the acquisition time. In addition, the longer FIFO
length results in an increased throughput delay and also influences the
3dB corner frequency. Generally, it’s recommended to use the lower
0
When configured in single rail mode 2 with AMI line code enabled,
The jitter attenuator is provided for narrow-band width jitter transfer
For applications which require line synchronization, the line clock is
The jitter attenuator integrates a FIFO which can accommodate a
In host mode, bit JABW in GCF determines the jitter attenuator 3dB
Cable Length
/ 75
-
-
-
-
-
Reserved
133ft. ABAM
266ft. ABAM
399ft. ABAM
533ft. ABAM
655ft. ABAM
Cable
INDUSTRIAL TEMPERATURE RANGES
Maximum Cable Loss (dB)
0.6
1.2
1.8
2.4
3.0
-
-
1