IDT82V2048 Integrated Device Technology, Inc., IDT82V2048 Datasheet - Page 25
![no-image](/images/manufacturer_photos/0/3/334/integrated_device_technology__inc__sml.jpg)
IDT82V2048
Manufacturer Part Number
IDT82V2048
Description
Manufacturer
Integrated Device Technology, Inc.
Datasheet
1.IDT82V2048.pdf
(61 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT82V2048BB
Manufacturer:
IDT
Quantity:
17
Company:
Part Number:
IDT82V2048BB
Manufacturer:
IDT
Quantity:
1 831
Company:
Part Number:
IDT82V2048BB
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT82V2048BBG
Manufacturer:
IDT
Quantity:
6
Company:
Part Number:
IDT82V2048BBG
Manufacturer:
IDT
Quantity:
413
Company:
Part Number:
IDT82V2048BBG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT82V2048DA
Manufacturer:
IDT
Quantity:
12 388
Company:
Part Number:
IDT82V2048DA
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT82V2048DA
Manufacturer:
IDT
Quantity:
20 000
Company:
Part Number:
IDT82V2048DAG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT82V2048DAG
Manufacturer:
IDT
Quantity:
20 000
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
Interrupt Enable
four kinds of interrupts are all reported by this pin. When the Interrupt
Mask register (LOSM , DFM, AISM and e-LBM) is set to ‘1’, the Inter-
rupt Status register (LOSI, DFI, AISI and e-LBI) is enabled respec-
tively. Whenever there is a transition (‘0’ to ‘1’ or ‘1’ to ‘0’) in the corre-
sponding Status register, the Interrupt Status register will change into
‘1’, which means an interrupt occurs, and there will be a transition
from high to low on INT. An external pull-up resistor of approximately
10k
of the four Interrupt Mask registers is set to ‘0’ (the power-on default
value is ‘0’), the corresponding Interrupt Status register is disabled
and the transition on status register is ignored.
Interrupt Clearing
AISI and e-LBI) are read to identify the interrupt source. And these
registers will be cleared to ‘0’ after the corresponding Status register
(LOS, DF, AIS and e-LBS) being read. The Status registers will be
cleared once the corresponding conditions are met.
The interrupt handling in the interrupt service routine is showed Fig-
ure-19.
The IDT82V2048 provides a latched interrupt output (INT) and the
When an interrupt occurs, the Interrupt Status registers (LOSI, DFI,
Pin INT is pulled High when there are no pending interrupt left.
is required to support the wire-OR operation of INT. When any
25
G.772 MONITORING
regular transceivers. In applications using only seven channels
(channels 1 to 7), channel 0 is configured to non-intrusively monitor
any of the other channels’ inputs or outputs on the line side. The
monitoring is non-intrusive per ITU-T G.772. Figure-20 shows the
Monitoring Principle. The receiver or transmitter path to be monitored
is configured by pin MC[0:3] in hardware mode or by PMON in host
mode (refer to Programming Information for details).
recovery circuit of channel 0. The monitored clock can output on RCLK0
which can be used as a timing interfaces derived from E1 signal. The
monitored data can be observed digitally at the output pin RCLK0,
RD0/RDP0 and RDN0. LOS detector is still in use in channel 0 for the
monitored signal.
Loopback. The signal which is being monitored will output on TTIP0 and
TRING0. The output signal can then be connected to a standard test
equipment with an E1 electrical interface for non-intrusive monitoring.
The eight channels of IDT82V2048 can all be configured to work as
The signal which is monitored goes through the clock and data
In monitoring mode, channel 0 can be configured to the Remote
INDUSTRIAL TEMPERATURE RANGES