IDT82V2048 Integrated Device Technology, Inc., IDT82V2048 Datasheet - Page 14

• Manufacturer Part Number: IDT82V2048
• Manufacturer: Integrated Device Technology, Inc.

TABLE - 2. ACTIVE CLOCK EDGE AND ACTIVE LEVEL
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
TABLE - 1a. SYSTEM INTERFACE CONFIGURATION (Hardware Mode)
CLOCK EDGES
selectable. If pin CLKE is Low, the active edge of RCLK is the rising
edge, as for SCLK, that is falling edge. On the contrary, if CLKE is High,
the active edge of RCLK is the falling edge and that of SCLK is rising
edge. Pins RDn/RDPn, CVn/RDNn and SDO are always active high, and
those output signals are valid on the active edge of RCLK and SCLK
respectively. See Table-2 for details. However, in dual rail mode without
clock recovery, pin CLKE is used to set the active level for RDPn/RDNn
raw slicing output: High for active high polarity and Low for active low. It
should be noted that data on pin SDI are always active high and is
sampled on the rising edge of SCLK. The data on pin TD/TDP or BPVI/
TDN are also always active high but is sampled on the falling edge of
TCLK, despite the level on CLKE.
TABLE - 1b. SYSTEM INTERFACE CONFIGURATION (Host Mode)
The active edge of RCLK and SCLK(serial interface clock) are also
clocked
clocked
clocked
clocked
clocked
clocked
MCLK
MCLK
H
L
H
L
H (
TDNn
pulse
pulse
pulse
pulse
pulse
Pin CLKE
H
TDNn
pulse
pulse
pulse
High
16 MCLK)
Low
CRSn in e-CRS
RCLK
RCLK
Clock recovery
0
0
0
1
-
-
RD/RDP and CV/RDN
Receive just slice the incoming data. Transmit is determined by the status of TCLKn.
Receive is power down. Transmit is determined by the status of TCLKn.
Active High
Active High
SINGn in e-SING
Hardware Mode
0
1
0
0
-
-
Host Mode
14
Slicer output
Active Low
Active High
Dual Rail with Clock Recovery
RECEIVER
transformer and are converted into RZ digital pulses by a data slicer.
Adaptation for attenuation is achieved using an integral peak detector
that sets the slicing levels. Clock and data are recovered from the
received RZ digital pulses by a digital phase-locked loop that provides
excellent jitter accommodation. After passing through the selectable jitter
attenuator, the recovered data are decoded using B8ZS/HDB3 or AMI
line code rules and clocked out of pin RDn in single rail mode, or
presented on RDPn/RDNn in an undecoded dual rail NRZ format. Loss
of signal, alarm indication signal, line code violations and excessive zero
are detected. The presence of programmable inband loopback codes
are also detected. These various changes in status may be enabled to
generate interrupts.
Peak Detector and Slicer
pulses. In data recovery mode, the raw positive slicer output appears on
In receive path, the line signals couple into RRINGn and RTIPn via a
The slicer determines the presence and polarity of the received
Single Rail mode 1
Interface
Receive just slice the incoming data.
Transmit is determined by the status of TCLKn.
Transmit is determined by the status of TCLKn.
Receive is power down.
SCLK Active High
SCLK
INDUSTRIAL TEMPERATURE RANGES
Dual Rail with Data Recovery
Dual Rail with Clock Recovery
SDO
Single Rail mode 1
Single Rail mode 2
Active High
Interface