IDT82V2048 Integrated Device Technology, Inc., IDT82V2048 Datasheet - Page 23

• Manufacturer Part Number: IDT82V2048
• Manufacturer: Integrated Device Technology, Inc.

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
Inband Loopback
agnosis. When this function is enabled, the chip will detect or generate
the Inband Loopback Code. There are two kinds of Inband Loopback
Code:Active Code and Deactive Code. If the Active Code is received
from the far end in a continuous 5.1 second, the chip can go into Re-
mote Loopback Mode (Figure-15) automatically. If the Deactive Code is
received from the far end in a continuous 5.1 second, the chip can quit
from the Remote Loopback mode automatically. The chip can also send
the Active Code and Deactive Code to the far end. Two function blocks
realize the Inband Loopback : IBLC Detector (Inband Loopback Code
Detector) and IBLC Generator ( Inband Loopback Code Generator).
e-LBCF register). If ALBE (bit 4, e-LBCF register) is set to 1, the chip
will go into or quit from the Remote Loopback mode automatically based
on the receipt of Inband Loopback Code. The length of the Active Code
is defined in LBAL[1:0] (bit 3-2, e-LBCF register); and the length of the
Deactive Code is defined in the LBDL[1:0] (bit 1-0, e-LBCF register).
The pattern of the Active Code is defined in the e-LBAC register, and
the pattern of the Deactive Code is defined in the e-LBDC register. The
above settings are globally effective for all the eight channels. The pres-
ence of Inband Loopback Code in each channel is reflected timely in the
e-LBS register. Any transition of each bit in the e-LBS register will be
reflected in the e-LBI register, and if enabled in the e-LBM register,
will generate an interrupt. The required sequence of programming
the Inband Loopback Code detection is : First, set the e-LBAC and e-
LBDC registers, followed by the e-LBM register. Finally, to activate
Inband Loopback detection, set the e-LBCF register.
the Inband Loopback Detector to define the length and pattern of Ac-
tive Code and Deactive Code. The length and pattern of the gener-
ated Active Code and Deactive Code can be different from the de-
tected Active Code and Deactive Code. The e-LBGS register deter-
mines sending Active Code or Deactive Code, and the e-LBGE acts
as a switch button to start or stop the sending of Inband Loopback
Code to the selected channels. Before sending Inband Loopback
Code, users should be sure that the e-LBCF register, the e-LBAC
register, the e-LBDC register and the e-LBSG register are configured
properly. The required sequence for configuring the Inband Loopback
Generator is: First, set the e-LBAC and e-LBDC registers, followed by
the e-LBCF register. Then, to select the Inband Loopback generator
set e-LBGS and then e-LBGE.
Inband Loopback is a function that facilitates the system remote di-
The detection of Inband Loopback Code is enabled by LBDE (bit 5,
The Inband Loopback Code Generator use the same registers as
The Inband Loopback Detection and the Inband Loopback Genera-
RRINGn
TRINGn
RTIPn
TTIPn
Detector
Peak
Driver
Line
Figure - 17c. TAOS with Analog Loopback
Slicer
Detector
LOS
CLK&Data
Recovery
(DPLL)
23
Waveform
Transmit
All Ones
Shaper
tion can not be used simultaneously. The Inband Loopback Code is
compatible with the specifications in T1.403, TA-TSY-000312 and TR-
TSY-000303.
interrupts):
HOST INTERFACES
in the device. The interface consists of serial host interface and
parallel host interface. By pulling pin MODE2 to VDDIO/2 or to High,
the device can be set to work in serial mode and in parallel mode
respectively.
Parallel Host Interface
MODE1 and MODE0 are used to select the operating mode of the
parallel host interface. When pin MODE1 is pulled to Low, the host
uses separate address bus and data bus. When High, multiplexed
address/data bus is used. When pin MODE0 is pulled to Low, the par-
allel host interface is configured for Motorola compatible hosts. When
High, for Intel compatible hosts. This is well described in the Pin De-
scription. The host interface pins in each operation mode is tabu-
lated in Table-12.
Example: 5-bit Loop-up/Loop-Down Detection (w/o interrupts):
(see note in register description for e-LBAC)
Set (in this order)
Example: 5-bit Loop-up/Loop-down Activation on Channel 1 (w/o
Set (in this order)
The host interface provides access to read and write the registers
The interface is compatible with Motorola or Intel host. Pins
One of Eight Identical Channels
Attenuator
Loop-up code: 11000
Loop-down code : 11100
e-LBAC (0x09) = 0xC6 (11000110)
e-LBDC (0x0A) = 0xE7 (11100111)
e-LBCF (0x08) = 0x30
Loop-up code: 11000
Loop-down code : 11100
e-LBAC (0x09) = 0xC6 (11000110)
e-LBDC (0x0A) = 0xE7 (11100111)
e-LBCF (0x08) = 0x00
e-LBGS (0x0E) = 0x00
e-LBGE (0x0F) = 0x02
Jitter
HDB3/AMI
HDB3/AMI
Encoder
Decoder
B8ZS/
B8ZS/
INDUSTRIAL TEMPERATURE RANGES
LOSn
BPVIn/TDNn
RDn/RDPn
CVn/RDNn
RCLKn
TCLKn
TDn/TDPn