IDT82V2048 Integrated Device Technology, Inc., IDT82V2048 Datasheet - Page 40

• Manufacturer Part Number: IDT82V2048
• Manufacturer: Integrated Device Technology, Inc.

JTAG DATA REGISTER
Device Identification Register (IDR)
the device revision, which can be used to verify the proper version or
revision number that has been used in the system under test. The IDR is
32 bits long and is partitioned as in Table-18. Data from the IDR is
shifted out to TDO LSB first.
IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
TABLE - 17. INSTRUCTION REGISTER DESCRIPTION
TABLE - 18. DEVICE IDENTIFICATION REGISTER DESCRIPTION
TABLE - 19. BOUNDARY SCAN REGISTER DESCRIPTION
IR CODE
The IDR can be set to define the producer number, part number and
000
100
110
111
BIT No.
12~27
28~31
1~11
BIT No.
0
10
11
12
13
14
0
1
2
3
4
5
6
7
8
9
Extest
Sample / Preload
Idcode
Bypass
INSTRUCTION
BIT SYMBOL
POUT0
POUT1
POUT2
POUT3
POUT4
POUT5
POUT6
POUT7
PIN0
PIN1
PIN2
PIN3
PIN4
PIN5
PIN6
The external test instruction allows testing of the interconnection to other devices. When the current
instruction is the EXTEST instruction, the boundary scan register is placed between TDI and TDO. The
signal on the input pins can be sampled by loading the boundary scan register using the Capture-DR state.
The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state.
The signal on the output pins can be controlled by loading patterns shifted in through input TDI into the
boundary scan register using the Update-DR state.
The sample instruction samples all the device inputs and outputs. For this instruction, the boundary scan
register is placed between TDI and TDO. The normal path between IDT82V2048 logic and the I/O pins is
maintained. Primary device inputs and outputs can be sampled by loading the boundary scan register using
the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using
the Shift-DR state.
The identification instruction is used to connect the identification register between TDI and TDO. The
device's identification code can then be shifted out using the Shift-DR state.
The bypass instruction shifts data from input TDI to output TDO with one TCK clock period delay. The
instruction is used to bypass the device.
Producer Number
Device Revision
COMMENTS
Part Number
Set to “1”
PIN SIGNAL
LP0
LP0
LP1
LP1
LP2
LP2
LP3
LP3
LP4
LP4
LP5
LP5
LP6
LP6
LP7
TYPE
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
40
Bypass Register (BR)
the TDI input and TDO output, bypassing the BSR to reduce test access
times.
Boundary Scan Register (BSR)
the digital I/O pins. The BSR is a 98 bits long shift register and is
initialized and read using the instruction EXTEST or SAMPLE/
PRELOAD. Each pin is related to one or more bits in the BSR. Please
refer to Table-19 for details of BSR bits and their functions.
TEST ACCESS PORT CONTROLLER
22 shows its state diagram A description of each state follows. Note
that the figure contains two main branches to access either the data or
instruction registers. The value shown next to each state transition in
this figure states the value present at TMS at each rising edge of TCK.
Please refer to Table-20 for details of the state description.
The BR consists of a single bit. It can provide a serial path between
The BSR can apply and read test patterns in parallel to or from all
The TAP controller is a 16-state synchronous state machine. Figure-
COMMENTS
COMMENTS
INDUSTRIAL TEMPERATURE RANGES