IDT82V2048 Integrated Device Technology, Inc., IDT82V2048 Datasheet - Page 15

• Manufacturer Part Number: IDT82V2048
• Manufacturer: Integrated Device Technology, Inc.

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
RDPn while the negative slicer output appears on RDNn. In clock and
data recovery mode, the slicer output is sent to Clock and Data Recov-
ery circuit for abstracting retimed data and optional decoding. The slicer
circuit has a built-in peak detector from which the slicing threshold is de-
rived. The slicing threshold is default to 50% (typical) of the peak value.
ered accurately by the receiver. To provide immunity from impulsive
noise, the peak detectors are held above a minimum level of 0.150 V
typically, despite the received signal level.
Clock and Data Recovery
Phase Locked Loop (DPLL). The DPLL is clocked 16 times of the
received clock rate, i.e. 24.704 MHz in T1 mode or 32.768 MHz in E1
mode. The recovered data and clock from DPLL is then sent to the
selectable Jitter Attenuator or decoder circuit for further processing.
channel basis by setting the bit CRSn in e-CRS. When bit CRSn is
defaulted to ‘0’, the corresponding channel operates in data and clock
recovery mode. The recovered clock is output on pin RCLKn and re-
timed NRZ data are output on pin RDPn/RDNn in dual rail mode or on
RDn in single rail mode. When CRSn is ‘1’, dual rail with data recovery
mode is enabled in the corresponding channel and the clock recovery
function is bypassed. In this condition, the analog line signal are
converted to RZ digital bit streams on the RDPn/RDNn pins and
internally connected to an EXOR which is fed to the RCLKn output for
external clock recovery applications.
dual rail with data recovery mode. In this case, e-CRS is ignored.
TABLE - 3. CONFIGURATION OF THE LINE CODE RULE
TABLE - 4. LOS CONDITION IN CLOCK RECOVERY MODE
Detected
Cleared
Signals with an attenuation of up to 12 dB (from 2.4V) can be recov-
The function of Clock and Data Recovery is accomplished by Digital
The clock recovery and data recovery mode can be selected on per
Moreover, Pulling MCLK to H level, all the receivers will enter the
LOS
LOS
CODE
L
H
Hardware Mode
Continuous
Amplitude
Amplitude
Intervals
Density
All channels in AMI
Line Code Rule
All channels in
HDB3/B8ZS
12.5% (16 marks in a sliding
128-bit period) with no more
exceed typ. 540mV (Vpp)
than 99 continuous zeros
below typ. 310mV (Vpp)
ANSI T1.231 for T1
175
CODE in GCF CODEn in e-CODE SINGn in e-SINGn
0
0
1
1
0
1
12.5% (4 marks in a sliding
32-bit period) with no more
than 15 continuous zeros
exceed typ.540mV (Vpp)
below typ. 310mV (Vpp)
0 / 1
0 / 1
15
0
1
1
0
STANDARD
B8ZS/HDB3/AMI Line Code Rule
when the device is configured in single rail mode. B8ZS rules for T1 or
HDB3 rules for E1 is enabled by setting bit CODE in register GCF (glo-
bal control configuration) to ‘0’ or pulling pin CODE to Low. AMI rule is
enabled by setting bit CODE in GCF to ‘1’ or pulling pin CODE to High.
All the setting above are effected to eight channels.
able by setting bit SINGn in e-SING to ‘1’ (to activate bit CODEn in e-
CODE) and programming bit CODEn to select line code rules in the cor-
responding channel: ‘0’ for B8ZS/HDB3, while ‘1’ for AMI. In this case,
the value in bit CODE in GCF or pin CODE for global control is unaf-
fected in the corresponding channel and only affect in other channels.
GCF, bit CODEn in e-CODE and pin CODE are ignored.
Loss of Signal (LOS) Detection
the received signal on Receiver line before the transformer (measured
on port A, B in Figure 12). The loss condition is reported by pulling pin
LOSn to high. In the same time, LOS alarm registers track LOS
condition. When LOS detected or cleared, an interrupt will generate if
not masked. In host mode, the detection supports the ANSI T1.231 for
T1 mode and ITU-G.775 and ETSI 300233 for E1 mode. In hardware
mode, it only supports the ITU-G.775 and ANSI T1.231 specification.
the signal level exceeds 540mV.
G.775 for E1
Selectable B8ZS/HDB3 or AMI line coding/decoding is provided
Individual line code rule selection for each channel, if need, is avail-
In dual rail mode, the decoder/encoder are bypassed. Bit CODE in
The configuration of the Line Code Rule is summarized in Table-3.
The Loss of Signal Detector monitors the amplitude and density of
Table-4 summarizes the conditions of LOS in clock recovery mode.
In data recovery mode, the LOS condition is cleared upon detecting
During LOS, the RDPn/RDNn output the sliced data when bit AISE in
32
Host Mode
0
1
0
1
1
1
12.5% (4 marks in a sliding
32-bit period) with no more
INDUSTRIAL TEMPERATURE RANGES
exceed typ. 540mV (Vpp)
than 15 continuous zeros
below typ. 310mV (Vpp)
ETSI 300233 for E1
2048 (1 ms)
All channels in HDB3/B8ZS
All channels in AMI
CHn in HDB3/B8ZS
Line Code Rule
CHn in AMI
Signal on
pin LOSn
H
L