IDT82V2048 Integrated Device Technology, Inc., IDT82V2048 Datasheet
IDT82V2048
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IDT82V2048 Summary of contents
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... Slicer Attenuator (DPLL) Peak Digital Detector Loopback Line Waveform Driver Shaper Attenuator Transmit All Ones Register Control Interface File Figure - 1. Block Diagram 1 IDT82V2048 B8ZS/ Jitter HDB3/AMI Decoder IBLC Remote Detector AIS Loopback Detector B8ZS/ Jitter HDB3/AMI Encoder IBLC Generator VDD IO VDDT ...
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... Transmit equalization is implemented with low-impedance output drivers that provide shaped waveforms to the transformer, guaranteeing template conformance. A jitter attenuator is integrated in the IDT82V2048 and can be switched into either the transmit path or the receive path for all chan- PIN CONFIGURATIONS BPVI4/TDN4 ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT PIN CONFIGURATIONS (CONTINUED RCLK TCLK RCLK TCLK RDP TDP RDP TDP RDN TDN RDN TDN VDDT VDDT VDDT VDDT TRING TTIP TRING TTIP ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT PIN DESCRIPTION Pin No. Name Type QFP144 BGA160 TTIP0 45 TTIP1 52 TTIP2 57 TTIP3 64 TTIP4 117 TTIP5 124 TTIP6 129 TTIP7 Analog 136 Output TRING0 46 TRING1 51 TRING2 58 TRING3 63 TRING4 118 TRING5 123 TRING6 130 TRING7 135 RTIP0 ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT PIN DESCRIPTION (CONTINUED) Pin No. Name Type QFP144 BGA160 TD0/TDP0 37 N2 TD1/TDP1 30 L2 TD2/TDP2 80 L13 TD3/TDP3 73 N13 TD4/TDP4 108 B13 TD5/TDP5 101 D13 TD6/TDP6 8 D2 TD7/TDP7 BPVI0/TDN0 38 N3 BPVI1/TDN1 31 L3 BPVI2/TDN2 79 L12 BPVI3/TDN3 72 N12 ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT PIN DESCRIPTION (CONTINUED) Pin No. Name Type QFP144 BGA160 RD0/RDP0 RD1/RDP1 33 M2 RD2/RDP2 Tri-state 77 M13 RD3/RDP3 70 P13 RD4/RDP4 111 A13 RD5/RDP5 104 C13 RD6/RDP6 5 C2 RD7/RDP7 142 A2 CV0/RDN0 41 P3 CV1/RDN1 34 M3 CV2/RDN2 76 M12 CV3/RDN3 ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT PIN DESCRIPTION (CONTINUED) Pin No. Name Type QFP144 BGA160 MODE2 (Pulled to VDDIO / 2) MODE1 MODE0 I 88 H12 /CODE CS /JAS I 87 J11 (Pulled to VDDIO / 2) Description Hardware/Host Control Mode MODE2: Control Mode Select 2 The signal on this pin determines which control mode is selected to control the device: ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT PIN DESCRIPTION (CONTINUED) Pin No. Name Type QFP144 BGA160 TS2: Template Select 2 TS2 J12 SCLK/ In hardware control mode, the signal on this pin is the most significant bit for the transmit template select. ALE/ AS Refer to Transmit Template of the Functional Description for details. ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT PIN DESCRIPTION (CONTINUED) Pin No. Name Type QFP144 BGA160 SDO O 83 K14 /RDY / ACK INT O 82 K13 Open Drain LP7/D7/AD7 I LP6/D6/AD6 27 J1 LP5/D5/AD5 26 J2 LP4/D4/AD4 Tri-state 25 J3 LP3/D3/AD3 24 J4 ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT PIN DESCRIPTION (CONTINUED) Pin No. Name Type QFP144 BGA160 MC3/ MC2/ MC1/ MC0/ 114 E14 CLKE I 115 E13 Description MCn: Performance Monitor Configuration 4~0 In hardware control mode, A4 must be connected to GND. MC[3:0] are used to select one transmitter or receiver of the channel for non-intrusive monitoring ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT PIN DESCRIPTION (CONTINUED) Pin No. Name Type QFP144 BGA160 TRST I 95 G12 Pullup TMS I 96 F11 Pullup TCK I 97 F14 TDO O 98 F13 Tri-state TDI I 99 F12 Pull G13 H13 VDDIO - G14 ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT FUNCTIONAL DESCRIPTION OVERVIEW The IDT82V2048 is a fully integrated octal short-haul line interface unit, which contains eight transmit and receive channels for use in either applications. The receiver performs clock and data recovery option, the raw sliced data (no retiming) can be output to the sys- tem ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT RTIPn RRINGn Peak Detector TTIPn Driver TRINGn RTIPn RRINGn Peak Detector TTIPn Line Driver TRINGn One of Eight Identical Channels LOS Detector CLK&Data Recovery Slicer Attenuator (DPLL) Line Waveform Attenuator Shaper Transmit All Ones Figure - 4. Dual Rail Interface with Data Recovery ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT TABLE - 1a. SYSTEM INTERFACE CONFIGURATION (Hardware Mode) MCLK TDNn clocked MCLK) clocked pulse H pulse L pulse TABLE - 1b. SYSTEM INTERFACE CONFIGURATION (Host Mode) MCLK TDNn CRSn in e-CRS clocked H clocked pulse clocked pulse clocked pulse H pulse L pulse TABLE - 2 ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT RDPn while the negative slicer output appears on RDNn. In clock and data recovery mode, the slicer output is sent to Clock and Data Recov- ery circuit for abstracting retimed data and optional decoding. The slicer circuit has a built-in peak detector from which the slicing threshold is de- rived ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT register GCF output all ones as AIS (alarm indication signal) when bit AISE is set to 1; The RCLKn is replaced by MCLK only if the AISE is set. Alarm Indication Signal Detection (AIS) Alarm Indication Signal is available only in host mode with clock recovery, as Table-5 shows ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT CLK RTIP 1 4 consecutive zeros RRING CLK RTIP 2 RRING TRANSMITTER In transmit path, data in NRZ (non return to zero) format are clocked into the device on TDn and encoded by AMI or HDB3/B8ZS line code rules when single rail mode is configured or pre-encoded data in NRZ format are input on TDPn and TDNn when dual rail mode is configured ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT The built-in waveform shaper use an internal high frequency clock which is 16XMCLK as clock reference. This function will be bypassed when MCLK is unavailable. 1.2 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 0 250 500 Time (ns) Figure - 10. DSX-1 Waveform Template 1.20 1.00 0.80 0.60 0.40 0.20 0.00 -0.20 -300 -200 -100 0 Time (ns) Figure - 11. CEPT Waveform Template TABLE - 7 ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT corner frequency and the shortest FIFO length that can still meet jitter attenuation requirements. TABLE - 8. GAP WIDTH LIMITATION FIFO Length Max. Gap Width 64 bit 32 bit TABLE - 9. OUTPUT JITTER SPECIFICATION T1 AT&T Pub 62411 GR-253-CODE TR-TSY-000009 TABLE - 10 ...
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... High, setting bit RPDNn in e-RPDN to ‘1’ will configure the corresponding receiver to power down. INTERFACE WITH 5V LOGIC The IDT82V2048 can interface directly with 5V TTL family devices. The internal input pads are tolerant to 5V output from TTL and CMOS family devices. ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT RTIPn RRINGn Peak Detector TTIPn Line Driver TRINGn RTIPn RRINGn Analog Loopback Detector TTIPn TRINGn RTIPn Slicer RRINGn Peak Detector TTIPn Line Driver TRINGn One of Eight Identical Channels LOS Detector CLK&Data Recovery Slicer (DPLL) ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT RTIPn RRINGn Peak Detector TTIPn Line Driver TRINGn RTIPn RRINGn Peak Detector TTIPn Line Driver TRINGn RTIPn RRINGn Peak Detector TTIPn Line Driver TRINGn One of Eight Identical Channels LOS Detector CLK&Data Jitter Slicer Recovery ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT RTIPn RRINGn Detector TTIPn TRINGn Inband Loopback Inband Loopback is a function that facilitates the system remote di- agnosis. When this function is enabled, the chip will detect or generate the Inband Loopback Code. There are two kinds of Inband Loopback Code:Active Code and Deactive Code ...
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... SCLK SDI R/W SDO NOTE: 1. While R/W=1, read from IDT82V2048; While R/W=0, write to IDT82V2048. 2. Ignored. Serial Host Interface By pulling pin MODE2 to VDDIO/2, the device operates in the serial host Mode. In this mode, the registers are accessible through a 16-bit word which contains an 8-bit command/address byte (bit R/W and 5- address-bit A1~A5, A6 and A7 are ignored) and a subsequent 8-bit data byte (D0~D7) ...
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... The interrupt handling in the interrupt service routine is showed Fig- ure-19. INDUSTRIAL TEMPERATURE RANGES G.772 MONITORING The eight channels of IDT82V2048 can all be configured to work as regular transceivers. In applications using only seven channels (channels 1 to 7), channel 0 is configured to non-intrusively monitor any of the other channels’ inputs or outputs on the line side. The monitoring is non-intrusive per ITU-T G ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT RTIPn RRINGn Detector TTIPn TRINGn G.772 Monitor RTIP0 RRING0 Detector TTIP0 TRING0 LOS Detector CLK&Data Slicer Recovery (DPLL) Peak Line Waveform Driver Shaper Transmit All Ones LOS Detector CLK&Data Slicer Recovery (DPLL) Peak Line ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT PROGRAMMING INFORMATION REGISTER LIST AND MAP There are 23 primary registers (including an Address Pointer Control Register), including 16 expanded registers in the device. Whatever the control interface is, 5 address bits are used to set the registers. In non-multiplexed parallel interface mode, the five dedicated address bits are A[4:0] ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT TABLE - 14. EXPANDED (INDIRECT ADDRESS MODE) REGISTER LIST Address serial parallel Hex interface interface A7-A1 A7-A0 00 XX00000 XXX00000 e-SING 01 XX00001 XXX00001 e-CODE 02 XX00010 XXX00010 e-CRS 03 XX00011 XXX00011 e-RPDN 04 XX00100 XXX00100 e-TPDN 05 XX00101 XXX00101 e-CZER 06 XX00110 XXX00110 e-CODV ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT TABLE - 15. PRIMARY REGISTER MAP Address Register R/W Default ID 00 Hex R/W Default ALB 01 Hex ALB 7 R/W Default RLB 02 Hex RLB 7 R/W Default TAO 03 Hex TAO 7 R/W Default LOS 04 Hex LOS 7 R/W Default DF 05 Hex R/W Default LOSM 06 Hex LOSM 7 R/W Default DFM ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT TABLE - 15. PRIMARY REGISTER MAP (CONTINUED) Address Register R/W Default TSIA 10 Hex R/W Default TS 11 Hex R/W Default OE 12 Hex R/W Default AIS 13 Hex R/W Default AISM 14 Hex AISM 7 R/W Default AISI 15 Hex AISI 7 R/W Default ADDP 1F Hex ADDP 7 R/W Default ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT TABLE - 16. EXPANDED (INDIRECT ADDRESS MODE) REGISTER MAP Address Register R/W Default e-SING 00 Hex SING 7 R/W Default e-CODE 01 Hex CODE 7 R/W Default e-CRS 02 Hex CRS 7 R/W Default e-RPDN 03 Hex RPDN 7 R/W Default e-TPDN 04 Hex TPDN 7 R/W Default e-CZER 05 Hex CZER 7 R/W Default ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT REGISTER DESCRIPTION Primary Register Description ID: Device ID Register (R, Address = 00 Hex) Symbol Position Default ID[7:0] ID.7 ALB: Analog Loopback Configuration Register (R/W, Address = 01 Hex) Symbol Position Default ALB[7:0] ALB.7 RLB: Remote Loopback Configuration Register (R/W, Address = 02 Hex) Symbol ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT LOSI: Loss of Signal Interrupt Status Register (R, Address = 08 Hex) Symbol Position LOSI[7:0] LOSI.7-0 DFI: Driver Fault Interrupt Status Register (R, Address = 09 Hex) Symbol Position Default DFI[7:0] DFI.7-0 RS: Software Reset Register (W, Address = 0A Hex) Symbol Position Default RS[7:0] RS.7 PMON: Performance Monitor Configuration Register (R/W, Address = 0B Hex) ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT ATAO: Automatic TAO Configuration Register (R/W, Address = 0E Hex) Symbol Position ATAO[7:0] ATAO.7-0 GCF: Global Configuration Register (R/W, Address = 0F Hex) Symbol Position Default - GCF.7 0 AISE GCF.6 0 SCPB GCF.5 0 CODE GCF.4 0 JADP GCF.3 0 JABW GCF.2 0 JACF[1:0] GCF.1-0 00 TSIA: Indirect Address Register for Transmit Template Select Registers (R/W, Address = 10 Hex) ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT TS: Transmit Template Select Register (R/W, Address = 11 Hex) Symbol Position Default - TS.7-3 00000 TS[2-0] TS.2-0 000 OE: Output Enable Configuration Register (R/W, Address = 12 Hex) Symbol Position OE[7:0] OE.7-0 AIS: Alarm Indication Signal Status Register (R, Address = 13 Hex) Symbol Position AIS[7:0] AIS.7-0 AISM : Alarm Indication Signal Interrupt Mask Register (R/W, Address = 14 Hex) ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT Expanded Register Description e-SING: Single Rail Mode Setting Register (R/W, Expanded Address = 00 Hex) Symbol Position Default SING[7:0] SING.7 e-CODE: Encoder/Decoder Selection Register (R/W, Expanded Address = 01 Hex) Symbol Position Default CODE[7:0] CODE.7 e-CRS: Clock Recovery Enable/Disable Selection Register (R/W, Expanded Address = 02 Hex) ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT e-LBCF: Inband Loopback Configuration Register (R/W, Expanded Address = 08 Hex) Symbol Position Default - LBCF.7-6 000 LBDE LBCF.5 0 ALBE LBCF.4 0 LBAL[1:0] LBCF.3-2 00 LBDL[1:0] LBCF.1-0 00 e-LBAC: Inband Loopback Activation Code Register (R/W, Expanded Address = 09 Hex) Symbol Position Default LBAC[7:0] LBAC ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT e-LBI: Inband Loopback Interrupt Status Register (R, Expanded Address = 0D Hex) Symbol Position Default LBI[7:0] LBI.7 e-LBGS: Inband Loopback Activation/Deactivation Code Generator Selection Register (R/W, Expanded Address = 0E Hex) Symbol Position Default LBGS[7:0] LBGS.7 e-LBGE: Inband Loopback Activation/Deactivation Code Generator Enable Register (R/W, Expanded Address = 0F Hex) ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT IEEE STD 1149.1 JTAG TEST AC- CESS PORT The IDT82V2048 supports the digital Boundary Scan Specification as described in the IEEE 1149.1 standards. The boundary scan architecture consists of data and instruction reg- isters plus a Test Access Port (TAP) controller. Control of the TAP is achieved through signals applied to the Test Mode Select (TMS) and Test Clock (TCK) input pins ...
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... Update-DR state. The sample instruction samples all the device inputs and outputs. For this instruction, the boundary scan register is placed between TDI and TDO. The normal path between IDT82V2048 logic and the I/O pins is 100 Sample / Preload maintained ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT TABLE - 19. BOUNDARY SCAN REGISTER DESCRIPTION (CONTINUED) BIT No. BIT SYMBOL 15 PIN7 16 PIOS 17 TCLK1 18 TDP1 19 TDN1 20 RCLK1 21 RDP1 22 RDN1 23 HZEN1 24 LOS1 25 TCLK0 26 TDP0 27 TDN0 28 RCLK0 29 RDP0 30 RDN0 31 HZEN0 32 LOS0 33 MODE1 34 LOS3 35 RDN3 36 RDP3 37 HZEN3 38 RCLK3 39 TDN3 ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT TABLE - 19. BOUNDARY SCAN REGISTER DESCRIPTION (CONTINUED) BIT No. BIT SYMBOL 56 CSB 57 MODE0 58 TCLK5 59 TDP5 60 TDN5 61 RCLK5 62 RDP5 63 RDN5 64 HZEN5 65 LOS5 66 TCLK4 67 TDP4 68 TDN4 69 RCLK4 70 RDP4 71 RDN4 72 HZEN4 73 LOS4 CLKE 76 LOS7 77 RDN7 78 RDP7 79 HZEN7 80 RCLK7 ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT TABLE - 20. TAP CONTROLLER STATE DESCRIPTION STATE In this state, the test logic is disabled. The device is set to normal operation. During initialization, the device initializes the instruction register with the IDCODE instruction. Test Logic Regardless of the original state of the controller, the controller enters the Test-Logic-Reset state when the TMS input is Reset held high for at least 5 rising edges of TCK ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT TABLE - 21. TAP CONTROLLER STATE DESCRIPTION (CONTINUED) STATE This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-IR state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the Exit1-IR controller enters the Pause-IR state ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT ABSOLUTE MAXIMUM RATING Symbol VDDA,VDDD Core Power Supply VDDIO0,VDDIO1 I/O Power Supply VDDT0-7 Transmit Power Supply Input Voltage, Any Digital Pin Vin Input Voltage, Any RTIP and RRING pin ESD Voltage, any pin Transient latch-up current, any pin ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT POWER CONSUMPTION Symbol E1, 3.3V, 75 Load E1, 3.3V, 120 Load E1, 5.0V, 75 Load E1, 5.0V, 120 Load T1, 3.3V, 100 Load T1, 5.0V, 100 Load NOTE: 1. Maximum power and current consumption over the full operating temperature and power supply voltage range. Includes all channels. ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT TRANSMITTER CHARACTERISTICS Symbol V Output pulse amplitudes 0-p E1, 75 load E1,120 load T1,100 load V Zero (space) level O-S E1, 75 load E1,120 load T1,100 load Transmit amplitude variation with supply Difference between pulse sequences for 17 consecutive pulses T Output Pulse Width at 50% of nominal amplitude ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT RECEIVER CHARACTERISTICS Symbol ATT Permissible Cable Attenuation (E1:@1024kHz, T1:@772KHz) IA Input Amplitude SIR Signal to Interference Ratio Margin SRE Data decision threshold (reference to peak input voltage) Data slicer threshold Analog loss of signal Threshold: Hysteresis: Allowable consecutive zeros before LOS E1, G ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT JITTER ATTENUATOR CHARACTERISTICS Symbol f Jitter Transfer Function Corner (–3dB) Frequency -3dB Host mode Hardware mode Jitter Attenuator E1: ( 400 Hz @ 100kHz T1: ( 1kHz @ 1.4kHz @ 70kHz td Jitter Attenuator Latency Delay 32bit FIFO: ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT TRANSCEIVER TIMING CHARACTERISTICS Symbol MCLK frequency E1: T1: MCLK tolerance MCLK duty cycle Transmit path TCLK frequency E1: T1: TCLK tolerance TCLK Duty Cycle t1 Transmit Data Setup Time t2 Transmit Data Hold Time Delay time of OE low to driver High Z ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT TCLK TNn/TDPn TDNn/BPVIn RCLK RDPn/RDn (CLKE = 1) RDNn/CVn RDPn/RDn (CLKE = 0) RDNn/CVn t1 t2 Figure - 24. Transmit System Interface Timing Figure - 25. Receive System Interface Timing 51 INDUSTRIAL TEMPERATURE RANGES t8 ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT JTAG TIMING CHARACTERISTICS Symbol t1 TCK Period t2 TMS to TCK setup Time TDI to TCK Setup Time t3 TCK to TMS Hold Time TCK to TDI Hold Time t4 TCK to TDO Delay Time TCK TMS TDI TDO Parameter Min Typ 200 ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT PARALLEL HOST INTERFACE TIMING CHARACTERISTICS INTEL MODE READ TIMING CHARACTERISTICS Symbol Active RD Pulse Width t1 Active CS to Active RD Setup Time t2 Inactive RD to Inactive CS Hold Time t3 t4 Valid Address to Inactive ALE Setup Time (in Multiplexed Mode) Invalid RD to Address Hold Time (in Non-Multiplexed Mode) ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT CS RD ALE(=1) A[7:0] D[7:0] RDY INT CS RD t11 ALE t4 ADDRESS AD[7:0] RDY INT t2 t1 t13 ADDRESS t6 t8 t15 Figure - 27. Non-Multiplexed Intel Mode Read Timing t2 t1 t12 t13 t16 t6 t8 t15 Figure - 28. Multiplexed Intel Mode Read Timing 54 INDUSTRIAL TEMPERATURE RANGES ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT INTEL MODE WRITE TIMING CHARACTERISTICS Symbol Active WR Pulse Width t1 Active CS to Active WR Setup Time t2 Inactive WR to Inactive CS Hold Time t3 t4 Valid Address to Latch Enable Setup Time (in Multiplexed Mode) Invalid WR to Address Hold Time (in Non-Multiplexed Mode) ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT MOTOROLA MODE READ TIMING CHARACTERISTICS Symbol Active DS Pulse Width t1 Active CS to Active DS Setup Time t2 Inactive DS to Inactive CS Hold Time t3 Valid Active DS Setup Time t4 Inactive Hold Time t5 Valid Address to Active DS Setup Time (in Non-Multiplexed Mode) ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT MOTOROLA MODE WRITE TIMING CHARACTERISTICS Symbol Active DS Pulse Width t1 Active CS to Active DS Setup Time t2 Inactive DS to Inactive CS Hold Time t3 Valid Active DS Setup Time t4 Inactive Hold Time t5 Valid Address to Active DS Setup Time (in Non-Multiplexed Mode) ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT SERIAL HOST INTERFACE TIMING CHARACTERISTICS Symbol t1 SCLK High Time t2 SCLK Low Time t3 Active CS to SCLK Setup Time t4 Last SCLK Hold Time to Inactive CS Time t5 CS Idle Time t6 SDI to SCLK Setup Time t7 SCLK to SDI Hold Time ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT JITTER TOLERANCE PERFORMANCE E1 JITTER TOLERANCE PERFORMANCE G.823 IDT82V2048 Test condition: PRBS 2^15-1; Line code rule HDB3 is used. T1 JITTER TOLERANCE PERFORMANCE AT&T62411 IDT82V2048 Test condition: QRSS; Line code rule B8ZS is used 100 1 1 ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT JITTER TRANSFER PERFORMANCE E1 JITTER TRANSFER PERFORMANCE G.736 IDT82V2048 Test condition: PRBS 2^15-1; Line code rule HDB3 is used. T1 JITTER TRANSFER PERFORMANCE AT&T62411 GR-253-CORE TR-TSY-000009 IDT82V2048 Test condition: QRSS; Line code rule B8ZS is used -19 ...
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... IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT ORDERING INFORMATION XXXXXXX IDT Device Type Data Sheet Document History 11/4/2001 pgs 11, 19 11/20/2001 pgs 12, 14, 18, 19, 27, 30, 36, 44, 45, 46, 58 11/28/2001 pgs. 5, 27, 30, 37 11/29/2001 pgs 12/5/2001 pgs. 9 12/24/2001 pgs.44, 45 1/5/2002 pgs ...