L9803 STMicroelectronics, L9803 Datasheet - Page 84

• Manufacturer Part Number: L9803
• Description: Super Smart Power Motor Driver With 8-bit Mcu, Ram, Eeprom, Adc, Wdg, Timers, Pwm And H-bridge Driver
• Manufacturer: STMicroelectronics

On-Chip Peripherals
Note:
84/126
Reset by software to discard all messages transmitted by the node. Allows remote and data
frames to share the same identifier.
Bit 3 = NRTX No Retransmission
−
Set by software to disable the retransmission of unsuccessful messages.
Cleared by software to enable retransmission of messages until success is met.
Bit 2 = FSYN Fast Synchronization
−
Set by software to enable a fast resynchronization when leaving standby mode, i.e. wait for
only 11 recessive bits in a row.
Cleared by software to enable the standard resynchronization when leaving standby mode,
i.e. wait for 128 sequences of 11 recessive bits.
Bit 1 = WKPS Wake-up Pulse
−
Set by software to generate a dominant pulse when leaving standby mode.
Cleared by software for no dominant wake-up pulse.
Bit 0 = RUN CAN Enable
−
Set by software to leave standby mode after 128 sequences of 11 recessive bits or just 11
recessive bits if FSYN is set.
Cleared by software to request a switch to the standby or low-power mode as soon as any
on-going transfer is complete. Read-back as 1 in the meantime to enable proper signalling
of the standby state. The CPU clock may therefore be safely switched OFF whenever RUN
is read as 0.
BAUD RATE PRESCALER REGISTER (BRPR)
Read/Write in Standby mode
Reset Value: 00h
RJW[1:0] determine the maximum number of time quanta by which a bit period may be
shortened or lengthened to achieve resynchronization.
t
BRP[5:0] determine the CAN system clock cycle time or time quanta which is used to build
up the individual bit timing.
t
Where t
The resulting baud rate can be computed by the formula:
Writing to this register is allowed only in Standby mode to prevent any accidental CAN
protocol violation through programming errors.
RJW
CAN
Read/Set/Clear
Read/Set/Clear
Read/Set/Clear
Read/Set/Clear
RJW1
= t
= t
7
CPU
CAN
CPU
* (RJW + 1)
* (BRP + 1)
= time period of the CPU clock.
RJW0
BR
BRP5
=
------------------------------------------------------------------------------------------------- -
t
CPU
×
BRP4
(
BRP
+
1
)
1
×
BRP3
(
BS1
+
BS2
BRP2
+
3
)
BRP1
BRP0
L9803
0