L9803 STMicroelectronics, L9803 Datasheet - Page 82

• Manufacturer Part Number: L9803
• Description: Super Smart Power Motor Driver With 8-bit Mcu, Ram, Eeprom, Adc, Wdg, Timers, Pwm And H-bridge Driver
• Manufacturer: STMicroelectronics

On-Chip Peripherals
Caution:
82/126
(ETX = 1).
Cleared by software.
Bit 3 = SCIF Status Change Interrupt Flag
−
Set by hardware to signal the reception of a dominant bit while in standby or a change from
error active to error passive and bus-off while in run. Also signals any receive error when
ESCI = 1.
Cleared by software.
Bit 2 = ORIF Overrun Interrupt Flag
−
Set by hardware to signal that a message could not be stored because no receive buffer
was available.
Cleared by software.
Bit 1 = TEIF Transmit Error Interrupt Flag
−
Set by hardware to signal that an error occurred during the transmission of the highest
priority message queued for transmission.
Cleared by software.
Bit 0 = EPND Error Interrupt Pending
−
Set by hardware when at least one of the three error interrupt flags SCIF, ORIF or TEIF is
set.
Reset by hardware when all error interrupt flags have been cleared.
Interrupt flags are reset by writing a "0" to the corresponding bit position. The appropriate
way consists in writing an immediate mask or the one’s complement of the register content
initially read by the interrupt handler. Bit manipulation instruction BRES should never be
used due to its read-modify-write nature.
INTERRUPT CONTROL REGISTER (ICR)
Read/Write
Reset Value: 00h
Bit 6 = ESCI Extended Status Change Interrupt
−
Set by software to specify that SCIF is to be set on receive errors also.
Cleared by software to set SCIF only on status changes and wake-up but not on all receive
errors.
Bit 5 = RXIE Receive Interrupt Enable
−
Set by software to enable an interrupt request whenever a message has been received free
of errors.
Cleared by software to disable receive interrupt requests.
Read/Clear
Read/Clear
Read/Clear
Read Only
Read/Set/Clear
Read/Set/Clear
7
0
ESCI
RXIE
TXIE
SCIE
ORIE
TEIE
ETX
L9803
0