L9803 STMicroelectronics, L9803 Datasheet - Page 83

• Manufacturer Part Number: L9803
• Description: Super Smart Power Motor Driver With 8-bit Mcu, Ram, Eeprom, Adc, Wdg, Timers, Pwm And H-bridge Driver
• Manufacturer: STMicroelectronics

L9803
Bit 4 = TXIE Transmit Interrupt Enable
−
Set by software to enable an interrupt request whenever a message has been successfully
transmitted.
Cleared by software to disable transmit interrupt requests.
Bit 3 = SCIE Status Change Interrupt Enable
−
Set by software to enable an interrupt request whenever the node’s status changes in run
mode or whenever a dominant pulse is received in standby mode.
Cleared by software to disable status change interrupt requests.
Bit 2 = ORIE Overrun Interrupt Enable
−
Set by software to enable an interrupt request whenever a message should be stored and
no receive buffer is avalaible.
Cleared by software to disable overrun interrupt requests.
Bit 1 = TEIE Transmit Error Interrupt Enable
−
Set by software to enable an interrupt whenever an error has been detected during
transmission of a message.
Cleared by software to disable transmit error interrupts.
Bit 0 = ETX Early Transmit Interrupt
−
Set by software to request the transmit interrupt to occur as soon as the arbitration phase
has been passed successfully.
Cleared by software to request the transmit interrupt to occur at the completion of the
transfer.
CONTROL/STATUS REGISTER (CSR)
Read/Write
Reset Value: 00h
Bit 6 = BOFF Bus-Off State
−
Set by hardware to indicate that the node is in bus-off state, i.e. the Transmit Error Counter
exceeds 255.
Reset by hardware to indicate that the node is involved in bus activities.
Bit 5 = EPSV Error Passive State
−
Set by hardware to indicate that the node is error passive.
Reset by hardware to indicate that the node is either error active (BOFF = 0) or bus-off.
Bit 4 = SRTE Simultaneous Receive/Transmit Enable
Set by software to enable simultaneous transmission and reception of a message passing
the acceptance filtering. Allows to check the integrity of the communication path.
Read/Set/Clear
Read/Set/Clear
Read/Set/Clear
Read/Set/Clear
Read/Set/Clear
Read Only
Read Only
7
0
BOFF
EPSV
SRTE
NRTX
−
Read/Set/Clear
FSYN
On-Chip Peripherals
WKPS
RUN
0
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