L9803 STMicroelectronics, L9803 Datasheet - Page 21

• Manufacturer Part Number: L9803
• Description: Super Smart Power Motor Driver With 8-bit Mcu, Ram, Eeprom, Adc, Wdg, Timers, Pwm And H-bridge Driver
• Manufacturer: STMicroelectronics

L9803
3.3
3.3.1
3.3.2
3.3.3
This flag is useful for distinguishing Safeguard Reset, Power On / Low Voltage Reset and
Watchdog Reset.
b7 = SGFL: Safeguard low flag. Set by an Oscillator Safeguard Reset generated for
frequency too low, cleared by software (writing zero) or Power On / Low Voltage Reset. This
flag is useful for distinguishing Safeguard Reset, Power On / Low Voltage Reset and
Watchdog Reset.
b5 = SFGEN: Safeguard enable when set. It’s cleared only by hardware after a reset.
b4 = CANDS: CAN Transceiver disable. When this bit is set the CAN transceiver goes in
Power Down Mode and does not work until this bit is reset. CANDS is 0 after reset so the
standard condition is with the transceiver enabled. This bit can be used by application
requiring low power consumption (see
b3,b2,b1 = not used
b0 = PIEN: PWMI input enable. When set, the PWMI input line is connected to Input
Capture 2 of Timer 2. Otherwise, ICAP2_2 is the alternate function of PA7. See
the explanation of this function.
Watchdog system (WDG)
Introduction
The Watchdog is used to detect the occurrence of a software fault, usually generated by
external interference or by unforeseen logical conditions, which causes the application
program to give up its normal sequence. The Watchdog circuit generates an MCU reset on
expiry of a programmed time period, unless the program refreshes the counter’s contents
before it is decremented to zero.
Main Features
Functional Description
The counter value stored in the CR register (bits T6:T0), is decremented every 12,288
machine cycles, and the length of the timeout period can be programmed by the user in 64
increments.
If the watchdog is activated (the WDGA bit is set) and when the 7-bit timer (bits T6:T0) rolls
over from 40h to 3Fh (T6 becomes cleared), it initiates a reset cycle pulling low the reset pin
for typically 500ns.
–
–
–
–
Programmable Timer (64 increments of 12,288 CPU clock)
Programmable Reset
reset (if watchdog activated) after an HALT instruction or when bit timer MSB
reaches zero
Watchdog Reset indicated by status flag.
Section 5.8
Clocks, Reset, Interrupts & Power saving modes
for details).
Figure 34
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