L9803 STMicroelectronics, L9803 Datasheet - Page 33

• Manufacturer Part Number: L9803
• Description: Super Smart Power Motor Driver With 8-bit Mcu, Ram, Eeprom, Adc, Wdg, Timers, Pwm And H-bridge Driver
• Manufacturer: STMicroelectronics

L9803
5
5.1
5.1.1
5.1.2
Note:
2
3
1
On-Chip Peripherals
I/O Ports
Introduction
The internal I/O ports allow the transfer of data through digital inputs and outputs, the
interrupt generation coming from an I/O and for specific pins, the input/output of alternate
signals for the on-chip peripherals (TIMERS...).
Each pin can be programmed independently as digital input (with or without interrupt
generation) or digital output.
Functional Description
Each port has 2 main registers:
and one optional register:
Each I/O pin may be programmed using the corresponding register bits in the DDR and OR
registers: bit X corresponding to pin X of the port. The same correspondence is used for the
DR register.
The following description takes into account the OR register, (for specific ports which do not
provide this register refer to the I/O Port Implementation section). The generic I/O block
diagram is shown in
Input Modes
The input configuration is selected by clearing the corresponding DDR register bit.
In this case, reading the DR register returns the digital value applied to the external I/O pin.
Different input modes can be selected by software through the OR register.
1. Writing the DR register modifies the latch value but does not affect the pin status.
2. When switching from input to output mode, the DR register has to be written first to drive
the correct level on the pin as soon as the port is configured as an output.
3. Do not use read/modify/write instructions (BSET or BRES) to modify the DR register
External interrupt function
When an I/O is configured as Input with Interrupt, an event on this I/O can generate an
external interrupt request to the CPU.
Each pin can independently generate an interrupt request. The interrupt sensitivity is
independently programmable using the sensitivity bits in the Miscellaneous register.
Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout
description and interrupt section). If several input pins are selected simultaneously as
interrupt source, these are logically NANDed. For this reason if one of the interrupt pins is
tied low, it masks the other ones.
–
–
–
Data Register (DR)
Data Direction Register (DDR)
Option Register (OR)
Figure
16.
On-Chip Peripherals
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