L9803 STMicroelectronics, L9803 Datasheet - Page 49

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L9803

Manufacturer Part Number
L9803
Description
Super Smart Power Motor Driver With 8-bit Mcu, Ram, Eeprom, Adc, Wdg, Timers, Pwm And H-bridge Driver
Manufacturer
STMicroelectronics
Datasheet

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L9803
The following procedure is recommended to prevent the OCFi bit from being set between
the time it is read and the write to the OCiR register:
Figure 25. Output Compare Block Diagram
Figure 26. Output Compare Timing Diagram, Internal Clock Divided by 2
Forced Compare Output capability
When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit
has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit=1). The
OCFi bit is then not set by hardware, and thus no interrupt request is generated.
FOLVLi bits have no effect in either One-Pulse mode or PWM mode.
16-bit
16 BIT FREE RUNNING
OC1R Register
OUTPUT COMPARE
OCFi AND OCMPi PIN (OLVLi=1)
OUTPUT COMPARE REGISTER
16-bit
Write to the OCiHR register (further compares are inhibited).
Read the SR register (first step of the clearance of the OCFi bit, which may be
already set).
Write to the OCiLR register (enables the output compare function and clears the
OCFi bit).
COMPARE REGISTER LATCH
CIRCUIT
OC2R Register
COUNTER
INTERNAL CPU CLOCK
16-bit
TIMER CLOCK
COUNTER
OC1E
OCIE
OC2E
OCF1
CPU
FFFC
FOLV2 FOLV1
writes
(Control Register 2) CR2
(Control Register 1) CR1
FFFD FFFD FFFE FFFF 0000
OCF2
CC1
(Status Register) SR
FFFF
OLVL2
CC0
0
0
OLVL1
0
FFFF
On-Chip Peripherals
Latch
Latch
1
2
OCMP2
OCMP1
Pin
Pin
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