L9803 STMicroelectronics, L9803 Datasheet - Page 75

• Manufacturer Part Number: L9803
• Description: Super Smart Power Motor Driver With 8-bit Mcu, Ram, Eeprom, Adc, Wdg, Timers, Pwm And H-bridge Driver
• Manufacturer: STMicroelectronics

L9803
5.6.2
5.6.3
Main Features
●
●
●
●
●
●
●
●
●
●
●
●
●
●
Functional Description
Frame Formats
A summary of all the CAN frame formats is given in
the standard frame format since the extended one is only acknowledged.
A message begins with a start bit called Start Of Frame (SOF). This bit is followed by the
arbitration field which contains the 11-bit identifier (ID) and the Remote Transmission
Request bit (RTR). The RTR bit indicates whether it is a data frame or a remote request
frame. A remote request frame does not have any data byte.
The control field contains the Identifier Extension bit (IDE), which indicates standard or
extended format, a reserved bit (ro) and, in the last four bits, a count of the data bytes
(DLC). The data field ranges from zero to eight bytes and is followed by the Cyclic
Redundancy Check (CRC) used as a frame integrity check for detecting bit errors.
The acknowledgement (ACK) field comprises the ACK slot and the ACK delimiter. The bit in
the ACK slot is placed on the bus by the transmitter as a recessive bit (logical 1). It is
overwritten as a dominant bit (logical 0) by those receivers which have at this time received
the data correctly. In this way, the transmitting node can be assured that at least one
receiver has correctly received its message. Note that messages are acknowledged by the
receivers regardless of the outcome of the acceptance test.
The end of the message is indicated by the End Of Frame (EOF). The intermission field
defines the minimum number of bit periods separating consecutive messages. If there is no
subsequent bus access by any station, the bus remains idle.
Support of CAN specification 2.0A and 2.0B passive
Three prioritized 10-byte Transmit/Receive message buffers
Two programmable global 12-bit message acceptance filters
Programmable baud rates up to 1 MBit/s
Buffer flip-flopping capability in transmission
Maskable interrupts for transmit, receive (one per buffer), error and wake-up
Automatic low-power mode after 20 recessive bits or on demand (standby mode)
Interrupt-driven wake-up from standby mode upon reception of dominant pulse
Optional dominant pulse transmission on leaving standby mode
Automatic message queuing for transmission upon writing of data byte 7
Programmable loop-back mode for self-test operation
Advanced error detection and diagnosis functions
Software-efficient buffer mapping at a unique address space
Scalable architecture.
Figure 38
for reference. It covers only
On-Chip Peripherals
75/126