L9803 STMicroelectronics, L9803 Datasheet - Page 25

• Manufacturer Part Number: L9803
• Description: Super Smart Power Motor Driver With 8-bit Mcu, Ram, Eeprom, Adc, Wdg, Timers, Pwm And H-bridge Driver
• Manufacturer: STMicroelectronics

L9803
3.5.2
3.5.3
3.5.4
External Reset
The NRESET pin is both an input and an open-drain output with integrated pull-up resistor.
When one of the internal Reset sources is active, the Reset pin is driven low to reset the
whole application.
Reset Operation
The duration of the Reset condition, which is also reflected on the output pin, is fixed at 4096
internal CPU Clock cycles. A Reset signal originating from an external source must have a
duration of at least 1.5 internal CPU Clock cycles in order to be recognised. At the end of the
Power-On Reset cycle, the MCU may be held in the Reset condition by an External Reset
signal. The NRESET pin may thus be used to ensure V
MCU can operate correctly before the user program is run. Following a Power-On Reset
event, or after exiting Halt mode, a 4096 CPU Clock cycle delay period is initiated in order to
allow the oscillator to stabilise and to ensure that recovery has taken place from the Reset
state.
During the Reset cycle, the device Reset pin acts as an output that is pulsed low. In its high
state, an internal pull-up resistor of about 300KΩ is connected to the Reset pin. This resistor
can be pulled low by external circuitry to reset the device.
Power-on Reset - Low Voltage Detection
The POR/LVD function generates a static reset when the supply voltage is below a
reference value. In this way, the Power-On Reset and Low Voltage Reset function are
provided, in order to keep the system in safe condition when the voltage is too low.
The Power-Up and Power-Down thresholds are different, in order to avoid spurious reset
when the MCU starts running and sinks current from the supply.
The LVD reset circuitry generates a reset when V
The POR/LVD function is explained in
Power-On Reset activates the reset pull up transistor performing a complete chip reset. In
the same way a reset can be triggered by the watchdog, by the safeguard or by external low
level at NRESET pin. An external capacitor connected between NRESET and ground can
extend the power on reset period if required.
–
–
V
V
ResetON
ResetOFF
when V
when V
DD
DD
is rising
is falling
Figure
Clocks, Reset, Interrupts & Power saving modes
11.
DD
is below:
DD
has risen to a point where the
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