L9803 STMicroelectronics, L9803 Datasheet - Page 44

• Manufacturer Part Number: L9803
• Description: Super Smart Power Motor Driver With 8-bit Mcu, Ram, Eeprom, Adc, Wdg, Timers, Pwm And H-bridge Driver
• Manufacturer: STMicroelectronics

On-Chip Peripherals
Note:
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16-bit read sequence: (from either the Counter Register or the Alternate Counter
Register).
The user must read the MSB first, then the LSB value is buffered automatically.
This buffered value remains unchanged until the 16-bit read sequence is completed, even if
the user reads the MSB several times.
After a complete reading sequence, if only the CLR register or ACLR register are read, they
return the LSB of the count value at the time of the read.
An overflow occurs when the counter rolls over from FFFFh to 0000h then:
●
●
If one of these conditions is false, the interrupt remains pending to be issued as soon as
they are both true.
Clearing the overflow interrupt request is done by:
1.
2.
The TOF bit is not cleared by accesses to ACLR register. This feature allows simultaneous
use of the overflow function and reads of the free running counter at random times (for
example, to measure elapsed time) without the risk of clearing the TOF bit erroneously.
The timer is not affected by WAIT mode.
In HALT mode, the counter stops counting until the mode is exited. Counting then resumes
from the previous count (MCU awakened by an interrupt) or from the reset count (MCU
awakened by a Reset).
External Clock
The external clock (where available) is selected if CC0=1 and CC1=1 in CR2 register.
The status of the EXEDG bit determines the type of level transition on the external clock pin
EXCLK that will trigger the free running counter.
The counter is synchronised with the falling edge of the internal CPU clock.
At least four falling edges of the CPU clock must occur between two consecutive active
edges of the external clock; thus the external clock frequency must be less than a quarter of
the CPU clock frequency.
The TOF bit of the SR register is set.
A timer interrupt is generated if:
–
–
Reading the SR register while the TOF bit is set.
An access (read or write) to the CLR register.
TOIE bit of the CR1register is set and
I bit of the CCR register is cleared.
At t0
At t0 +∆t
Beginning of the sequence
Sequence completed
Read LSB
Read MSB
instructions
Other
Returns the buffered
LSB value at t0
LSB is buffered
L9803