ST72344S4 STMicroelectronics, ST72344S4 Datasheet - Page 48

• Manufacturer Part Number: ST72344S4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72344S4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

Supply, reset and clock management
7.5.4
Note:
7.5.5
7.6
Note:
48/247
Internal low-voltage detector (LVD) reset
Two different reset sequences caused by the internal LVD circuitry can be distinguished:
●
●
The device RESET pin acts as an output that is pulled low when V
V
The LVD filters spikes on V
It is recommended to make sure that the V
device is exiting from Reset, to ensure the application functions properly.
Internal watchdog reset
The reset sequence generated by a internal Watchdog counter overflow is shown in
Figure
Starting from the Watchdog counter underflow, the device RESET pin acts as an output that
is pulled low during at least t
Figure 17. Reset sequences
System integrity management (SI)
The system integrity management block contains the low-voltage detector (LVD) and
auxiliary-voltage detector (AVD) functions. It is managed by the SICSR register.
A reset can also be triggered following the detection of an illegal opcode or prebyte code.
Refer to
DD
WATCHDOG
RESET
EXTERNAL
RESET
SOURCE
RESET PIN
<V
V
V
Power-on reset
Voltage-drop reset
IT+(LVD)
IT-(LVD)
IT-
17.
Illegal opcode reset on page 196
(falling edge) as shown in
V
Run
DD
ACTIVE PHASE
RESET
LVD
DD
w(RSTL)out
larger than t
Doc ID 12321 Rev 5
t
t
w(RSTL)out
h(RSTL)in
Figure
Run
.
ACTIVE
PHASE
for further details.
g(VDD)
SHORT EXT.
DD
17.
RESET
supply voltage rises monotonously when the
DELAY
to avoid parasitic resets.
t
h(RSTL)in
t
w(RSTL)out
Run
WATCHDOG UNDERFLOW
ACTIVE
PHASE
LONG EXT.
RESET
DD
ST72344xx ST72345xx
<V
INTERNAL RESET (256 or 4096 T
VECTOR FETCH
Run
IT+
(rising edge) or
ACTIVE
PHASE
WATCHDOG
RESET
t
w(RSTL)out
Run
CPU
)