ST72344S4 STMicroelectronics, ST72344S4 Datasheet - Page 180

• Manufacturer Part Number: ST72344S4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72344S4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

On-chip peripherals
Note:
180/247
Bit 1 = BusyW Busy on Write to RAM Buffer
Bit 0 = B/W Byte / Word Mode
When word mode is enabled, all interrupts should be masked while the word is being written
in RAM.
I
Reset value: 0000 0000 (00h)
Bit 7= NACK Non Acknowledge not followed by Stop
Bit 6 = BERR Bus error
Bit 5 = WF3 Write operation to Slave 3
2
C3S status register (I2C3SSR)
NACK
This bit is set by hardware when a Stop/ Restart is detected after a write operation. The
I2C3S peripheral is temporarily disabled till this bit is reset. This bit is cleared by
software. If this bit is not cleared before the next slave address reception, further
communication will be non-acknowledged. This bit is set to 1 when modifying any bits
in Control Register 2. Writing a 1 to this bit does not actually modify BusyW but
prevents accidentally clearing of the bit.
0: No BusyW event occurred
1: A Stop/ Restart is detected after a write operation
This control bit must be set by software before a word is updated in the RAM buffer and
cleared by hardware after completion of the word update. In Word mode the CPU
cannot be interrupted when it is modifying the LSB byte and MSB byte of the word. This
mode is to ensure the coherency of data stored as words.
0: Byte mode
1: Word mode
This bit is set by hardware when a non acknowledge returned by the master is not
followed by a Stop or Restart condition. It is cleared by software reading the SR register
or by hardware when the interface is disabled (PE=0).
0: No NACK error occurred
1: Non Acknowledge not followed by Stop
This bit is set by hardware when the interface detects a misplaced Start or Stop
condition. It is cleared by software reading SR register or by hardware when the
interface is disabled (PE=0).
The SCL line is not held low while BERR=1.
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
This bit is set by hardware on reception of the direction bit in the I
Slave 3. This bit is cleared when the status register is read when there is no
communication ongoing or when the peripheral is disabled (PE = 0)
0: No write operation to Slave 3
1: Write operation performed to Slave 3
7
BERR
WF3
Doc ID 12321 Rev 5
WF2
Read Only
WF1
RF3
ST72344xx ST72345xx
2
C address byte for
RF2
RF1
0