ST72344S4 STMicroelectronics, ST72344S4 Datasheet - Page 152

• Manufacturer Part Number: ST72344S4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72344S4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

On-chip peripherals
11.6.4
Note:
152/247
When the I
In this case, the value of the external pull-up resistor used depends on the application.
When the I
Figure 68.
Functional description
Refer to the CR, SR1 and SR2 registers in
By default the I
initiates a transmit or receive sequence.
First the interface frequency must be configured using the FRi bits in the OAR2 register.
Slave mode
As soon as a start condition is detected, the address is received from the SDA line and sent
to the shift register; then it is compared with the address of the interface or the General Call
address (if selected by software).
In 10-bit addressing mode, the comparison includes the header sequence (11110xx0) and
the two most significant bits of the address.
Header matched (10-bit mode only): the interface generates an acknowledge pulse if the
ACK bit is set.
SDA or SDAI
SCL or SCLI
2
2
C cell is enabled, the SDA and SCL ports must be configured as floating inputs.
C cell is disabled, the SDA and SCL ports revert to being standard I/O port pins.
I
2
2
C interface block diagram
C interface operates in Slave mode (M/SL bit is cleared) except when it
Clock control
Clock control register (CCR)
Status register 1 (SR1)
Status register 2 (SR2)
Data control
Control register (CR)
Doc ID 12321 Rev 5
Section
Own address register 1 (OAR1)
Own address register 2 (OAR2)
11.6.7. for the bit definitions.
Data register (DR)
Data shift register
Control logic
Comparator
Interrupt
ST72344xx ST72345xx