ST72344S4 STMicroelectronics, ST72344S4 Datasheet - Page 181

• Manufacturer Part Number: ST72344S4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72344S4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST72344xx ST72345xx
Bit 4 = WF2 Write operation to Slave 2
Bit 3 = WF1 Write operation to Slave 1
Bit 2 = RF3 Read operation from Slave 3
Bit 1= RF2 Read operation from Slave 2
Bit 0= RF1 Read operation from Slave 1
I
Reset value: 0000 0000 (00h)
Bits 7:0 = NB [7:0] Byte Count Register
2
C byte count register (I2C3SBCR)
NB7
This bit is set by hardware on reception of the direction bit in the I
Slave 2. This bit is cleared when the status register is read when there is no
communication ongoing or when the peripheral is disabled (PE = 0)
0: No write operation to Slave 2
1: Write operation performed to Slave 2
This bit is set by hardware on reception of the direction bit in the I
Slave 1. This bit is cleared by software when the status register is read when there is
no communication ongoing or by hardware when the peripheral is disabled (PE = 0).
0: No write operation to Slave 1
1: Write operation performed to Slave 1
This bit is set by hardware on reception of the direction bit in the I
Slave 3. It is cleared by software reading the SR register when there is no
communication ongoing. It is also cleared by hardware when the interface is disabled
(PE=0).
0: No read operation from Slave 3
1: Read operation performed from Slave 3
This bit is set by hardware on reception of the direction bit in the I
Slave 2. It is cleared by software reading the SR register when there is no
communication ongoing. It is also cleared by hardware when the interface is disabled
(PE=0).
0: No read operation from Slave 2
1: Read operation performed from Slave 2
This bit is set by hardware on reception of the direction bit in the I
Slave 1. It is cleared by software reading SR register when there is no communication
ongoing. It is also cleared by hardware when the interface is disabled (PE=0).
0: No read operation from Slave 1
1: Read operation performed from Slave 1
This register keeps a count of the number of bytes received or transmitted through any
of the three addresses. This byte count is reset after reception by a slave address of a
new transfer and is incremented after each byte is transferred. This register is not
limited by the full page length. It is also cleared by hardware when interface is disabled
(PE =0).
7
NB6
NB5
Doc ID 12321 Rev 5
NB4
Read only
NB3
NB2
On-chip peripherals
2
2
2
2
2
C address byte for
C address byte for
C address byte for
C address byte for
C address byte for
NB1
NB0
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