ST72344S4 STMicroelectronics, ST72344S4 Datasheet - Page 165

• Manufacturer Part Number: ST72344S4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72344S4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST72344xx ST72345xx
Note:
I
Reset value: 0000 0000 (00h)
Bits 7:0 = D[7:0] 8-bit Data Register.
●
●
I
Reset value: 0000 0000 (00h)
7-bit addressing mode
Bits 7:1 = ADD[7:1] Interface address.
Bit 0 = ADD0 Address direction bit.
Address 01h is always ignored.
10-bit addressing mode
Bit 7:0 = ADD[7:0] Interface address.
2
2
C data register (DR)
C own address register (OAR1)
ADD7
D7
These bits contain the byte to be received or transmitted on the bus.
Transmitter mode: byte transmission start automatically when the software writes in the
DR register.
Receiver mode: the first data byte is received automatically in the DR register using the
least significant bit of the address.
Then, the following data bytes are received one by one after reading the DR register.
These bits define the I
interface is disabled (PE=0).
This bit is don’t care, the interface acknowledges either 0 or 1. It is not cleared when
the interface is disabled (PE=0).
These are the least significant bits of the I
cleared when the interface is disabled (PE=0).
7
7
ADD6
D6
ADD5
2
D5
C bus address of the interface. They are not cleared when the
Doc ID 12321 Rev 5
ADD4
D4
Read / Write
Read / Write
2
C bus address of the interface. They are not
ADD3
D3
ADD2
D2
On-chip peripherals
ADD1
D1
ADD0
165/247
D0
0
0