ST72344S4 STMicroelectronics, ST72344S4 Datasheet - Page 243

• Manufacturer Part Number: ST72344S4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72344S4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST72344xx ST72345xx
16.4.2
16.5
16.5.1
16.5.2
16.5.3
Workaround
Disable the timer interrupt before disabling the timer. Again while enabling, first enable the
timer then the timer interrupts.
Perform the following to disable the timer:
Perform the following to enable the timer again:
SCI wrong break duration
Description
A single break character is sent by setting and resetting the SBK bit in the SCICR2 register.
In some cases, the break character may have a longer duration than expected:
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●
In the same way, as long as the SBK bit is set, break characters are sent to the TDO pin.
This may lead to generate one break more than expected.
Occurrence
The occurrence of the problem is random and proportional to the baudrate. With a transmit
frequency of 19200 baud (f
occurrence is around 1%.
Workaround
If this wrong duration is not compliant with the communication protocol in the application,
software can request that an Idle line be generated before the break character. In this case,
the break duration is always correct assuming the application is not doing anything between
the idle and the break. This can be ensured by temporarily disabling interrupts.
The exact sequence is:
●
●
●
●
TACR1 = 0x00h; // Disable the compare interrupt
TACSR |= 0x40; // Disable the timer
TACSR &= ~0x40; // Enable the timer
TACR1 = 0x40; // Enable the compare interrupt
20 bits instead of 10 bits if M=0
22 bits instead of 11 bits if M=1
Disable interrupts
Reset and Set TE (IDLE request)
Set and Reset SBK (Break request)
Re-enable interrupts
CPU
Doc ID 12321 Rev 5
=8 MHz and SCIBRR=0xC9), the wrong break duration
Known limitations
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