ST72344S4 STMicroelectronics, ST72344S4 Datasheet - Page 143

• Manufacturer Part Number: ST72344S4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72344S4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST72344xx ST72345xx
Note:
Note:
Note:
Note:
Bit 4 = IDLE Idle line detect.
The IDLE bit is not set again until the RDRF bit has been set itself (that is, a new idle line
occurs).
Bit 3 = OR Overrun error.
When this bit is set, the RDR register content is not lost but the shift register is overwritten.
Bit 2 = NF Noise flag.
This bit does not generate interrupt as it appears at the same time as the RDRF bit which
itself generates an interrupt.
Bit 1 = FE Framing error.
This bit does not generate an interrupt as it appears at the same time as the RDRF bit which
itself generates an interrupt. If the word currently being transferred causes both frame error
and overrun error, it is transferred and only the OR bit is set.
Bit 0 = PE Parity error.
cleared by a software sequence (an access to the SCISR register followed by a read to
the SCIDR register).
0: Data is not received
1: Received data is ready to be read
This bit is set by hardware when an Idle Line is detected. An interrupt is generated if
the ILIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to
the SCISR register followed by a read to the SCIDR register).
0: No Idle Line is detected
1: Idle Line is detected
This bit is set by hardware when the word currently being received in the shift register is
ready to be transferred into the RDR register while RDRF = 1. An interrupt is generated
if RIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to
the SCISR register followed by a read to the SCIDR register).
0: No Overrun error
1: Overrun error is detected
This bit is set by hardware when noise is detected on a received frame. It is cleared by
a software sequence (an access to the SCISR register followed by a read to the SCIDR
register).
0: No noise is detected
1: Noise is detected
This bit is set by hardware when a desynchronization, excessive noise or a break
character is detected. It is cleared by a software sequence (an access to the SCISR
register followed by a read to the SCIDR register).
0: No Framing error is detected
1: Framing error or break character is detected
This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by
a software sequence (a read to the status register followed by an access to the SCIDR
data register). An interrupt is generated if PIE = 1 in the SCICR1 register.
0: No parity error
1: Parity error
Doc ID 12321 Rev 5
On-chip peripherals
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