ST72344S4 STMicroelectronics, ST72344S4 Datasheet - Page 158

• Manufacturer Part Number: ST72344S4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72344S4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

On-chip peripherals
11.6.5
11.6.6
158/247
EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example
PE=1).
EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV9: EVF=1, ADD10=1, cleared by reading SR1 register followed by writing DR register.
Low-power modes
Table 64.
Interrupts
Figure 70. Event flags and interrupt generation
Table 65.
10-bit address sent event (Master mode)
End of byte transfer event
Address matched event (Slave mode)
Start bit generation event (Master mode)
Acknowledge failure event
Stop detection event (Slave mode)
Arbitration lost event (Multimaster configuration)
Bus error event
*
Mode
EVF can also be set by EV6 or an error from the SR2 register.
Wait
Halt
STOPF
ADD10
BERR
ARLO
ADSL
*
BTF
SB
AF
No effect on I
I
I
In HALT mode, the I
The I
from HALT mode” capability.
2
2
C interrupts cause the device to exit from Wait mode.
C registers are frozen.
Mode description
Interrupt events
Interrupt event
2
C interface resumes operation when the MCU is woken up by an interrupt with “exit
2
C interface.
2
C interface is inactive and does not acknowledge data on the bus.
(1)
Doc ID 12321 Rev 5
ITE
Description
Event flag
ADD10
STOPF
BERR
ARLO
ADSL
BTF
SB
AF
control bit
Enable
ITE
ST72344xx ST72345xx
Exit from
Wait
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Interrupt
Exit from
EVF
Halt
No
No
No
No
No
No
No
No