ST72344S4 STMicroelectronics, ST72344S4 Datasheet - Page 153

• Manufacturer Part Number: ST72344S4
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST72344S4

• Up To 16 Kbytes Program Memory: single voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention
• 256 Bytes Data Eeprom With Readout Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: crystal/ceramic resonator oscillators, high-accuracy internal RC oscillator or external clock
• 5 Power-saving Modes: Slow, Wait, Halt, Auto-wakeup from Halt and Active-halt
• 16-bit Timer A With: 1 input capture, 1 output compares, external clock input, PWM and pulse generator modes
• 16-bit Timer B With: 2 input captures, 2 output compares, PWM and pulse generator modes

ST72344xx ST72345xx
Address not matched: the interface ignores it and waits for another Start condition.
Address matched: the interface generates in sequence:
●
●
Then the interface waits for a read of the SR1 register, holding the SCL line low (see
Figure 69
Next, in 7-bit mode read the DR register to determine from the least significant bit (Data
Direction Bit) if the slave must enter Receiver or Transmitter mode.
In 10-bit mode, after receiving the address sequence the slave is always in receive mode. It
will enter transmit mode on receiving a repeated Start condition followed by the header
sequence with matching address bits and the least significant bit set (11110xx1).
Slave receiver
Following the address reception and after SR1 register has been read, the slave receives
bytes from the SDA line into the DR register via the internal shift register. After each byte the
interface generates in sequence:
●
●
Then the interface waits for a read of the SR1 register followed by a read of the DR register,
holding the SCL line low (see
Slave transmitter
Following the address reception and after SR1 register has been read, the slave sends
bytes from the DR register to the SDA line via the internal shift register.
The slave waits for a read of the SR1 register followed by a write in the DR register, holding
the SCL line low (see
When the acknowledge pulse is received:
●
Closing slave communication
After the last data byte is transferred a Stop Condition is generated by the master. The
interface detects this condition and sets:
●
Then the interface waits for a read of the SR2 register (see
EV4).
Error cases
●
●
Acknowledge pulse if the ACK bit is set.
EVF and ADSL bits are set with an interrupt if the ITE bit is set.
Acknowledge pulse if the ACK bit is set
EVF and BTF bits are set with an interrupt if the ITE bit is set.
The EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set.
EVF and STOPF bits with an interrupt if the ITE bit is set.
BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the
EVF and the BERR bits are set with an interrupt if the ITE bit is set.
If it is a Stop then the interface discards the data, released the lines and waits for
another Start condition.
If it is a Start then the interface discards the data and waits for the next slave address
on the bus.
AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set with
an interrupt if the ITE bit is set.
The AF bit is cleared by reading the I2CSR2 register. However, if read before the
completion of the transmission, the AF flag will be set again, thus possibly generating a
Transfer sequencing EV1).
Figure 69
Doc ID 12321 Rev 5
Figure 69
Transfer sequencing EV3).
Transfer sequencing EV2).
Figure 69
Transfer sequencing
On-chip peripherals
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