P89LPC915_916_917 NXP Semiconductors, P89LPC915_916_917 Datasheet - Page 50

• Manufacturer Part Number: P89LPC915_916_917
• Description: The P89LPC915/916/917 are single-chip microcontrollers, available in low-cost packages,based on a high performance processor architecture that executes instructions in two tofour clocks, six times the rate of standard 80C51 devices
• Manufacturer: NXP Semiconductors

NXP Semiconductors
P89LPC915_916_917_5
Product data sheet
Fig 21. Watchdog timer in Watchdog mode (WDTE = 1)
(1) Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a feed
watchdog
sequence.
oscillator
MOV WFEED1, #0A5H
MOV WFEED2, #05AH
PCLK
8.25.1 Software reset
8.25.2 Dual data pointers
8.24 Watchdog timer
8.25 Additional features
The watchdog timer causes a system reset when it underflows as a result of a failure to
feed the timer prior to the timer reaching its terminal count. It consists of a programmable
12-bit prescaler, and an 8-bit down-counter. The down-counter is decremented by a tap
taken from the prescaler. The clock source for the prescaler is either the PCLK or the
nominal 400 kHz watchdog oscillator. The watchdog timer can only be reset by a
power-on reset. When the watchdog feature is disabled, it can be used as an interval timer
and may generate an interrupt.
Feeding the watchdog requires a two-byte sequence. If PCLK is selected as the watchdog
clock and the CPU is powered down, the watchdog is disabled. The watchdog timer has a
time-out period that ranges from a few s to a few seconds. Please refer to the
P89LPC915/916/917 User’s Manual for more details.
The SRST bit in AUXR1 gives software the opportunity to reset the processor completely,
as if an external reset or watchdog reset had occurred. Care should be taken when writing
to AUXR1 to avoid accidental software resets.
The dual Data Pointers (DPTR) provides two different Data Pointers to specify the address
used with certain instructions. The DPS bit in the AUXR1 register selects one of the two
Data Pointers. Bit 2 of AUXR1 is permanently wired as a logic 0 so that the DPS bit may
be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register,
without the possibility of inadvertently altering other bits in the register.
WDCON (A7H)
32
PRE2
PRESCALER
Rev. 05 — 15 December 2009
PRE1
8-bit microcontrollers with accelerated two-clock 80C51 core
PRE0
Figure 21
SHADOW REGISTER
-
shows the watchdog timer in Watchdog mode.
-
P89LPC915/916/917
8-BIT DOWN
WDL (C1H)
COUNTER
WDRUN
WDTOF
WDCLK
© NXP B.V. 2009. All rights reserved.
002aaa905
reset
(1)
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