P89LPC915_916_917 NXP Semiconductors, P89LPC915_916_917 Datasheet - Page 36

• Manufacturer Part Number: P89LPC915_916_917
• Description: The P89LPC915/916/917 are single-chip microcontrollers, available in low-cost packages,based on a high performance processor architecture that executes instructions in two tofour clocks, six times the rate of standard 80C51 devices
• Manufacturer: NXP Semiconductors

NXP Semiconductors
P89LPC915_916_917_5
Product data sheet
8.13.1.1 Quasi-bidirectional output configuration
8.13.1 Port configurations
8.13 I/O ports
The P89LPC916 and P89LPC917 devices have three I/O ports: Port 0, Port 1, and Port 2.
The exact number of I/O pins available depends upon the clock and reset options chosen,
as shown in
Table 11.
[1]
The P89LPC915 has two I/O ports: Port 0 and Port 1. The exact number of I/O pins
available depends upon the clock and reset options chosen, as shown in
Table 12.
[1]
All but three I/O port pins on the P89LPC915/916/917 may be configured by software to
one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 port
outputs), push-pull, open drain, and input-only. Two configuration registers for each port
select the output type for each port pin.
Quasi-bidirectional output type can be used as both an input and output without the need
to reconfigure the port. This is possible because when the port outputs a logic HIGH, it is
weakly driven, allowing an external device to pull the pin LOW. When the pin is driven
LOW, it is driven strongly and able to sink a fairly large current. These features are
somewhat similar to an open-drain output except that there are three pull-up transistors in
the quasi-bidirectional output that serve different purposes.
Clock source
RC oscillator or watchdog
oscillator
External clock input
Clock source
RC oscillator or watchdog
oscillator
External clock input
1. P1.5 (RST) can only be an input and cannot be configured.
2. P1.2 (SCL/T0) and P1.3 (SDA/INT0) may only be configured to be either input-only or
Required for operation above 12 MHz.
Required for operation above 12 MHz.
open-drain.
Number of I/O pins available (P89LPC916 and P89LPC917)
Number of I/O pins available (P89LPC915)
Table
11.
Rev. 05 — 15 December 2009
8-bit microcontrollers with accelerated two-clock 80C51 core
Reset option
No external reset (except during
power-up)
External RST pin supported
No external reset (except during
power-up)
External RST pin supported
Reset option
No external reset (except during
power-up)
External RST pin supported
No external reset (except during
power-up)
External RST pin supported
P89LPC915/916/917
[1]
[1]
© NXP B.V. 2009. All rights reserved.
Number of I/O
pins (16-pin
package)
14
13
13
12
Number of I/O
pins (14-pin
package)
12
11
11
10
Table
12.
36 of 75