P89LPC915_916_917 NXP Semiconductors, P89LPC915_916_917 Datasheet - Page 32

• Manufacturer Part Number: P89LPC915_916_917
• Description: The P89LPC915/916/917 are single-chip microcontrollers, available in low-cost packages,based on a high performance processor architecture that executes instructions in two tofour clocks, six times the rate of standard 80C51 devices
• Manufacturer: NXP Semiconductors

NXP Semiconductors
P89LPC915_916_917_5
Product data sheet
8.6 External clock input option
8.7 CCLK wake-up delay
8.8 CCLK modification: DIVM register
In this configuration, the processor clock is derived from an external source driving the
CLKIN pin. The rate may be from 0 Hz up to 18 MHz.
When using an external clock input frequency above 12 MHz, the reset input
function of P1.5 must be enabled. An external circuit is required to hold the device
in reset at power-up until V
removed V
an external clock input frequency above 12 MHz, in some applications, an external
brownout detect circuit may be required to hold the device in reset when V
below the minimum specified operating voltage.
The P89LPC915/916/917 has an internal wake-up timer that delays the clock until it
stabilizes. The delay is 224 OSCCLK cycles plus 60 s to 100 s.
The OSCCLK frequency can be divided down up to 510 times by configuring a dividing
register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the
CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can
retain the ability to respond to events that would not exit Idle mode by executing its normal
program at a lower rate. This can also allow bypassing the oscillator start-up time in cases
where Power-down mode would otherwise be used. The value of DIVM may be changed
by the program at any time without interrupting code execution.
Fig 11. Block diagram of oscillator control
OSCILLATOR
(7.3728 MHz)
OSCILLATOR
WATCHDOG
CLKIN
(400 kHz)
RC
DD
GENERATOR
BAUD RATE
will fall below the minimum specified operating voltage. When using
RCCLK
Rev. 05 — 15 December 2009
8-bit microcontrollers with accelerated two-clock 80C51 core
DD
UART
has reached its specified level. When system power is
RCCLK
XCLK
TIMERS 1 AND 0
DIVM
peripheral clock
P89LPC915/916/917
OSCCLK
I
2
2
C
RTCS1:0
CCLK
PCLK
(P89LPC916)
SPI
ADC1/DAC1
© NXP B.V. 2009. All rights reserved.
WDT
CPU
RTC
CLKOUT
002aaa831
DD
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falls