P89LPC915_916_917 NXP Semiconductors, P89LPC915_916_917 Datasheet - Page 43

• Manufacturer Part Number: P89LPC915_916_917
• Description: The P89LPC915/916/917 are single-chip microcontrollers, available in low-cost packages,based on a high performance processor architecture that executes instructions in two tofour clocks, six times the rate of standard 80C51 devices
• Manufacturer: NXP Semiconductors

NXP Semiconductors
P89LPC915_916_917_5
Product data sheet
8.19.10 The 9
8.20 I
If double buffering is disabled TB8 can be written before or after SBUF is written, as long
as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until
the bit is shifted out, as indicated by the TI interrupt.
If double buffering is enabled, TB must be updated before SBUF is written, as TB8 will be
double-buffered together with SBUF data.
I
to the bus, and it has the following features:
A typical I
provides a byte-oriented I
2
2
Fig 14. I
C-bus uses two wires (SDA and SCL) to transfer information between devices connected
•
•
•
•
•
•
C-bus serial interface
Bidirectional data transfer between masters and slaves
Multi master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
The I
th
bit (bit 8) in double buffering (Modes 1, 2 and 3)
2
2
2
C-bus may be used for test and diagnostic purposes.
C-bus configuration is shown in
C-bus configuration
I
2
C-bus
P1.3/SDA
Rev. 05 — 15 December 2009
8-bit microcontrollers with accelerated two-clock 80C51 core
2
I
2
C-bus interface that supports data transfers up to 400 kHz.
C MCU
P1.2/SCL
OTHER DEVICE
WITH I
R PU
Figure
INTERFACE
2
P89LPC915/916/917
C-BUS
14. The P89LPC915/916/917 device
R PU
OTHER DEVICE
WITH I
INTERFACE
2
C-BUS
002aab410
© NXP B.V. 2009. All rights reserved.
SDA
SCL
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