ADUC7060 Analog Devices, ADUC7060 Datasheet - Page 97

• Manufacturer Part Number: ADUC7060
• Description: Low-Power, Precision Analog Microcontroller, Dual ?-? ADCs, Flash/EE, ARM7TDMI
• Manufacturer: Analog Devices

Specifications of ADUC7060

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 10
• Sram (bytes): 4096Bytes
• Gpio Pins: 14
• Adc # Channels: 10
• Other: 14 Bit DAC,PWM

SPI REGISTERS
The following MMR registers control the SPI interface: SPISTA, SPIRX, SPITX, SPIDIV, and SPICON.
SPI Status Register
SPISTA Register
Name:
Address:
Default value:
Access:
Function:
Table 106. SPISTA MMR Bit Designations
Bit
15:12
11
10:8
7
6
5
4
3:1
0
Name
SPIREX
SPIRXFSTA[2:0]
SPIFOF
SPIRXIRQ
SPITXIRQ
SPITXUF
SPITXFSTA[2:0]
SPIISTA
SPISTA
0xFFFF0A00
0x00000000
Read only
This 32-bit MMR contains the status of the SPI interface in both master and slave modes.
SPI receive FIFO status bits.
SPI receive IRQ status bit.
SPI transmit IRQ status bit.
SPI transmit FIFO underflow.
SPI transmit FIFO status bits.
Description
Reserved bits.
SPI receive FIFO excess bytes present. This bit is set when there are more bytes in the receive FIFO than
indicated in the SPIMDE bits in SPICON.
This bit is cleared when the number of bytes in the FIFO is equal to or less than the number in SPIMDE.
[000] = receive FIFO is empty.
[001] = 1 valid byte in the FIFO.
[010] = 2 valid bytes in the FIFO.
[011] = 3 valid bytes in the FIFO.
[100] = 4 valid bytes in the FIFO.
SPI receive FIFO overflow status bit.
Set when the receive FIFO was already full when new data was loaded to the FIFO. This bit generates an
interrupt except when SPIRFLH is set in SPICON.
Cleared when the SPISTA register is read.
Set when a receive interrupt occurs. This bit is set when SPITMDE in SPICON is cleared and the required
number of bytes has been received.
Cleared when the SPISTA register is read.
Set when a transmit interrupt occurs. This bit is set when SPITMDE in SPICON is set and the required number
of bytes has been transmitted.
Cleared when the SPISTA register is read.
This bit is set when a transmit is initiated without any valid data in the transmit FIFO. This bit generates an
interrupt except when SPITFLH is set in SPICON.
Cleared when the SPISTA register is read.
[000] = transmit FIFO is empty.
[001] = 1 valid bytes in the FIFO.
[010] = 2 valid bytes in the FIFO.
[011] = 3 valid bytes in the FIFO.
[100] = 4 valid bytes in the FIFO.
SPI interrupt status bit.
Set to 1 when an SPI based interrupt occurs.
Cleared after reading SPISTA.
Rev. C | Page 97 of 108
ADuC7060/ADuC7061