ADUC7060 Analog Devices, ADUC7060 Datasheet - Page 96

• Manufacturer Part Number: ADUC7060
• Description: Low-Power, Precision Analog Microcontroller, Dual ?-? ADCs, Flash/EE, ARM7TDMI
• Manufacturer: Analog Devices

Specifications of ADUC7060

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 10
• Sram (bytes): 4096Bytes
• Gpio Pins: 14
• Adc # Channels: 10
• Other: 14 Bit DAC,PWM

ADuC7060/ADuC7061
SERIAL PERIPHERAL INTERFACE
The ADuC706x integrates a complete hardware serial
peripheral interface (SPI) on chip. SPI is an industry standard,
synchronous serial interface that allows eight bits of data to be
synchronously transmitted and simultaneously received, that is,
full duplex up to a maximum bit rate of 5.12 Mbps.
The SPI port can be configured for master or slave operation
and typically consists of four pins: MISO, MOSI, SCLK, and SS .
MISO (MASTER IN, SLAVE OUT) PIN
The MISO pin is configured as an input line in master mode
and an output line in slave mode. The MISO line on the master
(data in) should be connected to the MISO line in the slave
device (data out). The data is transferred as byte wide (8-bit)
serial data, most significant bit first.
MOSI (MASTER OUT, SLAVE IN) PIN
The MOSI pin is configured as an output line in master mode
and an input line in slave mode. The MOSI line on the master
(data out) should be connected to the MOSI line in the slave
device (data in). The data is transferred as byte wide (8-bit)
serial data, most significant bit first.
SCLK (SERIAL CLOCK I/O) PIN
The master serial clock (SCL) synchronizes the data being
transmitted and received through the MOSI SCLK period.
Therefore, a byte is transmitted/received after eight SCLK
periods. The SCLK pin is configured as an output in master
mode and as an input in slave mode.
In master mode, polarity and phase of the clock are controlled
by the SPICON register, and the bit rate is defined in the
SPIDIV register as follows:
The maximum speed of the SPI clock is independent of the
clock divider bits.
GP0CON0 = BIT0 + BIT4 + BIT8 + BIT12;
GP0KEY1 = 0x7;
GP0CON1 &=~ BIT1;
GP0KEY2 = 0x13;
f
SERIAL
CLOCK
=
2
×
1 (
+
f
UCLK
SPIDIV
)
//Select SPI/I
//Write to GP0KEY1
//Select SPI functionality for P0.0 to P0.3
//Write to GP0KEY2
Rev. C | Page 96 of 108
In slave mode, the SPICON register must be configured with
the phase and polarity of the expected input clock. The slave
accepts data from an external master up to 5.12 Mbps.
In both master and slave modes, data transmit on one edge of
the SCLK signal and sample on the other. Therefore, it is
important that the polarity and phase be configured the same
for the master and slave devices.
SLAVE SELECT (P0.0/SS) INPUT PIN
In SPI slave mode, a transfer is initiated by the assertion of
on the P0.0/ SS pin, which is an active low input signal. The SPI
port then transmits and receives 8-bit data until the transfer is
concluded by deassertion of
input.
In SPI master mode, SS is an active low output signal. It asserts
itself automatically at the beginning of a transfer and deasserts
itself upon completion.
CONFIGURING EXTERNAL PINS FOR SPI
FUNCTIONALITY
The SPI pins of the ADuC706x device are represented by the
P0[0:3] function of the following pins:
•
•
•
•
To configure P0.0 to P0.3 for SPI mode, Bit 0, Bit 4, Bit 8, and
Bit 12 of the GP0CON0 register must be set to 1. Bit 1 of the
GP0CON1 must be set to 1. Note that to write to GP0CON1,
the GP0KEY1 register must be set to 0x7 immediately before
writing to GP0CON1. Also, the GP0KEY2 register must be set
to 0x13 immediately after writing to GP0CON1. The following
code example shows this in detail:
2
C alternative function for P0[0...3]
P0.0/ SS is the slave chip select pin. In slave mode, this pin
is an input and must be driven low by the master. In
master mode, this pin is an output and goes low at the
beginning of a transfer and high at the end of a transfer.
P0.1/SCLK/SCL is the SCLK pin.
P0.2/MISO is the master in, slave out (MISO) pin.
P0.3/MOSI/SDA is the master out, slave in (MOSI) pin.
SS . In slave mode, SS is always an
SS