ADUC7060 Analog Devices, ADUC7060 Datasheet - Page 33

• Manufacturer Part Number: ADUC7060
• Description: Low-Power, Precision Analog Microcontroller, Dual ?-? ADCs, Flash/EE, ARM7TDMI
• Manufacturer: Analog Devices

Specifications of ADUC7060

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 10
• Sram (bytes): 4096Bytes
• Gpio Pins: 14
• Adc # Channels: 10
• Other: 14 Bit DAC,PWM

RESET
There are four kinds of resets: external reset, power-on reset,
watchdog reset, and software reset. The RSTSTA register
indicates the source of the last reset and can be written by user
code to initiate a software reset event.
The bits in this register can be cleared to 0 by writing to the
RSTCLR MMR at 0xFFFF0234. The bit designations in
RSTCLR mirror those of RSTSTA. These registers can be used
during a reset exception service routine to identify the source of
the reset. The implications of all four kinds of reset events are
tabulated in Table 30.
RSTSTA Register
Name:
Address:
Default value:
Access:
Function:
Table 30. Device Reset Implications
RESET
POR
Watchdog
Software
External Pin
Yes
Reset
External Pins to
Default State
Yes
Yes
Yes
RSTSTA
Depends on type of reset
Read and write
This 8-bit register indicates the source of the
last reset event and can be written by user code
to initiate a software reset.
0xFFFF0230
Kernel
Executed
Yes
Yes
Yes
Yes
Reset All
External MMRs
(Excluding RSTSTA)
Yes
Yes
Yes
Yes
Rev. C | Page 33 of 108
RSTCLR Register
Name:
Address:
Access:
Function:
Table 29. RSTSTA/RSTCLR MMR Bit Designations
Bit
7:4
3
2
1
0
1
Peripherals
Reset
Yes
Yes
Yes
Yes
clear this bit generates a software reset.
If the software reset bit in RSTSTA is set, any write to RSTCLR that does not
RSTCLR
Write only
This 8-bit write only register clears the corres-
ponding bit in RSTSTA.
Description
Not used. These bits are not used and always
read as 0.
External reset.
Automatically set to 1 when an external reset
occurs.
This bit is cleared by setting the corresponding bit
in RSTCLR.
Software reset.
This bit is set to 1 by user code to generate a soft-
ware reset.
This bit is cleared by setting the corresponding bit
in RSTCLR.
Watchdog timeout.
Automatically set to 1 when a watchdog timeout
occurs.
Cleared by setting the corresponding bit in RSTCLR.
Power-on reset.
Automatically set when a power-on reset occurs.
Cleared by setting the corresponding bit in RSTCLR.
0xFFFF0234
Watchdog
Timer Reset
Yes
No
No
No
1
ADuC7060/ADuC7061
RAM
Valid
Yes/No
Yes
Yes
Yes
RSTSTA
(Status After
Reset Event)
RSTSTA[0] = 1
RSTSTA[1] = 1
RSTSTA[2] = 1
RSTSTA[3] = 1