ADUC7060 Analog Devices, ADUC7060 Datasheet - Page 22

• Manufacturer Part Number: ADUC7060
• Description: Low-Power, Precision Analog Microcontroller, Dual ?-? ADCs, Flash/EE, ARM7TDMI
• Manufacturer: Analog Devices

Specifications of ADUC7060

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 10
• Sram (bytes): 4096Bytes
• Gpio Pins: 14
• Adc # Channels: 10
• Other: 14 Bit DAC,PWM

ADuC7060/ADuC7061
such as C, it is necessary to ensure that the stack does not overflow.
This is dependent on the performance of the compiler that is used.
When an exception occurs, some of the standard registers are
replaced with registers specific to the exception mode. All
exception modes have replacement banked registers for the
stack pointer (R13) and the link register (R14) as represented
in Figure 9. The FIQ mode has more registers (R8 to R12)
supporting faster interrupt processing. With the increased
number of noncritical registers, the interrupt can be processed
without the need to save or restore these registers, thereby
reducing the response time of the interrupt handling process.
More information relative to the programmer’s model and the
ARM7TDMI core architecture can be found in ARM7TDMI
technical and ARM architecture manuals available directly from
ARM Ltd.
INTERRUPT LATENCY
The worst-case latency for an FIQ consists of the longest time
that the request can take to pass through the synchronizer, plus
the time for the longest instruction to complete (the longest
instruction is an LDM) that loads all the registers including the
PC, plus the time for the data abort entry, plus the time for FIQ
entry. At the end of this time, the ARM7TDMI is executing the
instruction at 0x1C (FIQ interrupt vector address). The maximum
total time is 50 processor cycles, or just over 4.88 μs in a system
using a continuous 10.24 MHz processor clock. The maximum
IRQ latency calculation is similar but must allow for the FIQ
having higher priority, which can delay entry into the IRQ
handling routine for an arbitrary length of time. This time can be
reduced to 42 cycles if the LDM command is not used; some
compilers have an option to compile without using this command.
Another option is to run the part in Thumb mode where this
time is reduced to 22 cycles.
The minimum latency for FIQ or IRQ interrupts is five cycles.
This consists of the shortest time that the request can take through
the synchronizer plus the time to enter the exception mode.
USER MODE
R15 (PC)
CPSR
R10
R11
R12
R13
R14
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
SPSR_FIQ
R10_FIQ
R11_FIQ
R12_FIQ
R13_FIQ
R14_FIQ
R8_FIQ
R9_FIQ
Figure 9. Register Organization
MODE
FIQ
SPSR_SVC
R13_SVC
R14_SVC
MODE
SVC
SPSR_ABT
R13_ABT
R14_ABT
ABORT
MODE
USABLE IN USER MODE
SYSTEM MODES ONLY
SPSR_IRQ
R13_IRQ
R14_IRQ
MODE
IRQ
UNDEFINED
SPSR_UND
R13_UND
R14_UND
MODE
Rev. C | Page 22 of 108
Note that the ARM7TDMI initially (first instruction) runs in
ARM (32-bit) mode when an exception occurs. The user can
immediately switch from ARM mode to Thumb mode if required,
for example, when executing interrupt service routines.
MEMORY ORGANIZATION
The ARM7, a von Neumann architecture MCU core, sees
memory as a linear array of 232-byte locations. As shown in
Figure 10, the ADuC706x maps this into four distinct user
areas: a memory area that can be remapped, an SRAM area, a
Flash/EE area, and a memory mapped register (MMR) area.
The first 30 kB of this memory space is used as an area into
which the on-chip Flash/EE or SRAM can be remapped. Any
access, either reading or writing, to an area not defined in the
memory map results in a data abort exception.
Memory Format
The ADuC706x memory organization is configured in little
endian format: the least significant byte is located in the lowest
byte address and the most significant byte in the highest byte
address (see Figure 11).
SRAM
The ADuC706x features 4 kB of SRAM, organized as 1024 ×
32 bits, that is, 1024 words located at 0x40000. The RAM space
can be used as data memory as well as volatile program space.
ARM code can run directly from SRAM at full clock speed
given that the SRAM array is configured as a 32-bit wide memory
array. SRAM is read/writable in 8-, 16-, and 32-bit segments.
Remap
The ARM exception vectors are all situated at the bottom of the
memory array, from Address 0x00000000 to Address 0x00000020.
BIT 31
0xFFFF0000
0x00080000
0x00040000
0x00000000
BYTE 3
B
7
3
.
.
.
0xFFFFFFFF
0x00087FFF
0x00040FFF
0x00007FFF
BYTE 2
Figure 11. Little Endian Format
A
6
2
.
.
.
Figure 10. Memory Map
32 BITS
BYTE 1
MMRs
RESERVED
FLASH/EE
RESERVED
SRAM
RESERVED
REMAPPABLE MEMORY SPACE
(FLASH/EE OR SRAM)
9
5
1
.
.
.
BYTE 0
8
4
0
.
.
.
BIT 0
0xFFFFFFFF
0x00000004
0x00000000