ADUC7060 Analog Devices, ADUC7060 Datasheet - Page 88

• Manufacturer Part Number: ADUC7060
• Description: Low-Power, Precision Analog Microcontroller, Dual ?-? ADCs, Flash/EE, ARM7TDMI
• Manufacturer: Analog Devices

Specifications of ADUC7060

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 10
• Sram (bytes): 4096Bytes
• Gpio Pins: 14
• Adc # Channels: 10
• Other: 14 Bit DAC,PWM

ADuC7060/ADuC7061
Table 96. I2CMCON MMR Bit Designations
Bit
15:9
8
7
6
5
4
3
2
1
0
Name
I2CMCENI
I2CNACKENI
I2CALENI
I2CMTENI
I2CMRENI
I2CMSEN
I2CILEN
I2CBD
I2CMEN
Description
Reserved. These bits are reserved and should not be written to.
I
Set this bit to enable an interrupt on detecting a stop condition on the I
Clear this interrupt source.
I
Set this bit to enable interrupts when the I
Clear this interrupt source.
I
Set this bit to enable interrupts when the I
Clear this interrupt source.
I
Set this bit to enable interrupts when the I
Clear this interrupt source.
I
Set this bit to enable interrupts when the I
Cleared by user to disable interrupts when the I
I
Set this bit to 1 to enable clock stretching. When SCL is low, setting this bit forces the device to hold SCL low until
I2CMSEN is cleared. If SCL is high, setting this bit forces the device to hold SCL low after the next falling edge.
Clear this bit to disable clock stretching.
I
Set this bit to enable loopback test mode. In this mode, the SCL and SDA signals are connected internally to their
respective input signals.
Cleared by user to disable loopback mode.
I
Set this bit to allow the device to compete for control of the bus even if another device is currently driving a start
condition.
Clear this bit to back off until the I
I
Set by user to enable the I
Cleared to disable the I
2
2
2
2
2
2
2
2
2
C transmission complete interrupt enable bit.
C no acknowledge (NACK) received interrupt enable bit.
C arbitration lost interrupt enable bit.
C transmit interrupt enable bit.
C receive interrupt enable bit.
C master SCL stretch enable bit.
C internal loopback enable.
C master backoff disable bit.
C master enable bit.
2
C master mode.
2
C master mode.
2
C bus becomes free.
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2
2
2
2
C master receives a no acknowledge.
C master did not gain control of the I
C master has transmitted a byte.
C master receives data.
2
C master is receiving data.
2
C bus.
2
C bus.